Marek Vasut f2f3782ead arm: socfpga: Define NAND reset bit ...

Define the NAND reset bit and fix the ordering of the macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

2015-12-22 21:30:02 +01:00

..

base_addr_a10.h

ARM: socfpga: arria10: add base address map for Arria10

2015-11-30 13:30:19 +01:00

base_addr_ac5.h

ARM: socfpga: rename the cyclone5 and arria5 base address file

2015-11-30 13:30:19 +01:00

clock_manager.h

arm: socfpga: clock: Clean up pll_config.h

2015-08-08 14:14:06 +02:00

dwmmc.h

mmc: dw_mmc: Probe the MMC from OF

2015-09-04 11:54:20 +02:00

fpga_manager.h

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freeze_controller.h

…

gpio.h

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nic301.h

…

reset_manager.h

arm: socfpga: Define NAND reset bit

2015-12-22 21:30:02 +01:00

scan_manager.h

arm: socfpga: scan: Add code to get FPGA ID

2015-08-08 14:14:30 +02:00

scu.h

…

sdram.h

ddr: altera: sequencer: Wrap misc remaining macros

2015-08-08 14:14:29 +02:00

system_manager.h

arm: socfpga: fix up a questionable macro for SDMMC

2015-12-20 03:44:56 +01:00

timer.h

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