Stefan Herbrechtsmeier 7a0bc18b63 fpga: zynq: Remove post config info message for SPL ...

The drivers informs the user that a post config was not run after FPGA
configuration. This message is unnecessary in SPL because the
ps7_post_config function is called via spl_board_prepare_for_boot
function before jump_to_image_no_args function from board_init_r
function.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

2022-09-12 12:03:17 +02:00

..

ACEX1K.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

altera.c

fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

2020-10-09 17:53:12 +08:00

cyclon2.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

fpga.c

fpga: add fpga_compatible2flag

2022-07-26 09:34:21 +02:00

intel_sdm_mb.c

arm: socfpga: soc64: Add ATF support for FPGA reconfig driver

2021-01-15 17:48:37 +08:00

ivm_core.c

common: Drop log.h from common header

2020-05-18 21:19:18 -04:00

Kconfig

fpga: add option for loading FPGA secure bitstreams

2022-07-26 08:42:16 +02:00

lattice.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

Makefile

fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

2020-10-09 17:53:12 +08:00

socfpga_arria10.c

socfpga: arria10: Wait for fifo empty after writing bitstream

2022-07-01 14:57:14 +08:00

socfpga_gen5.c

arm: socfpga: Convert system manager from struct to defines

2020-01-07 14:38:33 +01:00

socfpga.c

WS cleanup: remove trailing empty lines

2021-09-30 08:08:56 -04:00

spartan2.c

fpga: xilinx: pass compatible flags to load() callback

2022-07-26 09:34:21 +02:00

spartan3.c

fpga: xilinx: pass compatible flags to load() callback

2022-07-26 09:34:21 +02:00

stratixII.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

stratixv.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

versalpl.c

fpga: xilinx: pass compatible flags to load() callback

2022-07-26 09:34:21 +02:00

virtex2.c

fpga: xilinx: pass compatible flags to load() callback

2022-07-26 09:34:21 +02:00

xilinx.c

fpga: xilinx: pass compatible flags to load() callback

2022-07-26 09:34:21 +02:00

zynqmppl.c

fpga: zynqmp: support loading encrypted bitfiles

2022-07-26 09:34:21 +02:00

zynqpl.c

fpga: zynq: Remove post config info message for SPL

2022-09-12 12:03:17 +02:00