Kumar Gala 6d8565a1ed ppc/8xxx: Misc DDR related fixes ...

* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2009-09-15 21:30:08 -05:00

..

common_timing_params.h

FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

2008-08-27 02:05:58 +02:00

ctrl_regs.c

ppc/8xxx: Misc DDR related fixes

2009-09-15 21:30:08 -05:00

ddr1_dimm_params.c

fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT

2009-06-12 09:15:50 -05:00

ddr2_dimm_params.c

fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT

2009-06-12 09:15:50 -05:00

ddr3_dimm_params.c

ppc/8xxx: Misc DDR related fixes

2009-09-15 21:30:08 -05:00

ddr.h

fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT

2009-06-12 09:15:50 -05:00

lc_common_dimm_params.c

fsl-ddr: add the DDR3 SPD infrastructure

2009-03-30 13:33:50 -05:00

main.c

85xx, 86xx: Add common board_add_ram_info()

2009-07-22 09:43:48 -05:00

Makefile

fsl-ddr: add the DDR3 SPD infrastructure

2009-03-30 13:33:50 -05:00

options.c

fsl-ddr: add the DDR3 SPD infrastructure

2009-03-30 13:33:50 -05:00

util.c

85xx, 86xx: Add common board_add_ram_info()

2009-07-22 09:43:48 -05:00