Robert Hancock a0549f7390 fpga: virtex2: Add additional clock cycles after DONE assertion ...

Some Xilinx FPGA configuration options can result in the startup
sequence extending past the end of the FPGA bitstream. Continue applying
CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure
the startup sequence is complete, as recommended by Xilinx.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2019-07-30 10:20:06 +02:00

..

ACEX1K.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

altera.c

arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

2018-12-20 17:12:25 +01:00

cyclon2.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

fpga.c

cmd: fpga: Add support to load secure bitstreams

2018-06-01 11:37:31 +02:00

ivm_core.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

Kconfig

fpga: virtex2: added Kconfig option

2019-07-30 10:20:06 +02:00

lattice.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

Makefile

arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

2018-12-20 17:12:25 +01:00

socfpga_arria10.c

fpga: arria10: Fix error in fpga pin configuration

2019-07-21 12:47:13 +02:00

socfpga_gen5.c

arm: socfpga: fpga: fix type of local variable

2018-10-31 01:41:10 +01:00

socfpga.c

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2018-05-07 09:34:12 -04:00

spartan2.c

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2018-05-07 09:34:12 -04:00

spartan3.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

stratix10.c

ARM: socfpga: stratix10: Return valid error code from FPGA driver

2019-02-18 13:00:54 +01:00

stratixII.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

stratixv.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

virtex2.c

fpga: virtex2: Add additional clock cycles after DONE assertion

2019-07-30 10:20:06 +02:00

xilinx.c

fpga: zynqmp: Add secure bitstream loading for ZynqMP

2018-06-01 11:37:31 +02:00

zynqmppl.c

fpga: zynqmp: show an error message when FPGA programming fails

2019-01-24 10:03:43 +01:00

zynqpl.c

arm: zynq: Add an info message about post config

2019-04-16 11:51:34 +02:00