Robert Hancock a0549f7390 fpga: virtex2: Add additional clock cycles after DONE assertion ...

Some Xilinx FPGA configuration options can result in the startup
sequence extending past the end of the FPGA bitstream. Continue applying
CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure
the startup sequence is complete, as recommended by Xilinx.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2019-07-30 10:20:06 +02:00

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ACEX1K.c

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altera.c

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cyclon2.c

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fpga.c

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ivm_core.c

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Kconfig

fpga: virtex2: added Kconfig option

2019-07-30 10:20:06 +02:00

lattice.c

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Makefile

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socfpga_arria10.c

fpga: arria10: Fix error in fpga pin configuration

2019-07-21 12:47:13 +02:00

socfpga_gen5.c

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socfpga.c

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spartan2.c

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spartan3.c

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stratix10.c

ARM: socfpga: stratix10: Return valid error code from FPGA driver

2019-02-18 13:00:54 +01:00

stratixII.c

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stratixv.c

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virtex2.c

fpga: virtex2: Add additional clock cycles after DONE assertion

2019-07-30 10:20:06 +02:00

xilinx.c

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zynqmppl.c

fpga: zynqmp: show an error message when FPGA programming fails

2019-01-24 10:03:43 +01:00

zynqpl.c

arm: zynq: Add an info message about post config

2019-04-16 11:51:34 +02:00