Tingting Meng d0bf7bebfd arm: socfpga: socfpga_soc64: Enable LMB_ARCH_MEM_MAP ...

LMB_ARCH_MEM_MAP is enabled, and lmb_arch_add_memory() is introduced to
correctly handle memory reservations for the second and third DDR
memory banks.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>

2025-04-22 11:47:40 +08:00

..

include/mach

arm: socfpga: soc64: Enable F2S bridge reset support

2025-04-22 11:47:39 +08:00

altera-sysmgr.c

arm: socfpga: agilex5: Add new driver model for system manager in Agilex5

2025-02-25 10:53:31 -06:00

board.c

arm: socfpga: socfpga_soc64: Enable LMB_ARCH_MEM_MAP

2025-04-22 11:47:40 +08:00

ccu_ncore3.c

arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU

2025-02-25 10:53:56 -06:00

clock_manager_agilex5.c

…

clock_manager_agilex.c

…

clock_manager_arria10.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

clock_manager_gen5.c

…

clock_manager_n5x.c

…

clock_manager_s10.c

…

clock_manager.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

firewall.c

…

fpga_manager.c

…

freeze_controller.c

…

Kconfig

arm: socfpga: Disable GIC for Agilex5

2025-02-25 10:53:46 -06:00

lowlevel_init_soc64.S

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

mailbox_s10.c

arm: socfpga: mailbox: Notify SDM on HPS code execution stages

2025-04-22 11:47:39 +08:00

Makefile

configs: Enable VAB flow for Agilex5 SoCFPGA boards

2025-04-22 11:47:40 +08:00

misc_arria10.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

misc_gen5.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

misc_soc64.c

arm: socfpga: soc64: Update SoC64 CPU info

2025-04-22 11:47:40 +08:00

misc.c

ddr: altera: Add DDR driver for Agilex5 series

2025-02-25 10:54:01 -06:00

mmu-arm64_s10.c

arm: socfpga: agilex5: Add MMU mapping region

2025-04-22 11:47:40 +08:00

pinmux_arria10.c

…

qts-filter-a10.sh

…

qts-filter.sh

…

reset_manager_arria10.c

…

reset_manager_gen5.c

…

reset_manager_s10.c

arm: socfpga: soc64: Enable F2S bridge reset support

2025-04-22 11:47:39 +08:00

scan_manager.c

…

secure_reg_helper.c

…

secure_vab.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

smc_api.c

arm: socfpga: smc: Add memory coherency support to mailbox command

2025-02-25 10:54:00 -06:00

spl_a10.c

…

spl_agilex5.c

arm: socfpga: spl: Notify SDM on FSBL execution

2025-04-22 11:47:39 +08:00

spl_agilex.c

arm: socfpga: spl: Notify SDM on FSBL execution

2025-04-22 11:47:39 +08:00

spl_gen5.c

…

spl_n5x.c

arm: socfpga: spl: Notify SDM on FSBL execution

2025-04-22 11:47:39 +08:00

spl_s10.c

arm: socfpga: spl: Notify SDM on FSBL execution

2025-04-22 11:47:39 +08:00

spl_soc64.c

arm: socfpga: soc64: Add support for board_boot_order()

2025-02-25 10:54:04 -06:00

system_manager_gen5.c

…

system_manager_soc64.c

…

timer_s10.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

timer.c

…

vab.c

…

wrap_handoff_soc64.c

arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device

2025-02-25 10:53:47 -06:00

wrap_iocsr_config.c

…

wrap_pinmux_config.c

…

wrap_pll_config_soc64.c

arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11 11:44:47 -06:00

wrap_pll_config.c

…

wrap_sdram_config.c

…