b85fe01d7d
Add a new driver to control the USB 2.0 PHY reset controller on the Renesas RZ/G2L and related SoCs. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Renesas Electronics Corporation
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <renesas/rzg2l-usbphy.h>
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#include <reset-uclass.h>
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#include <reset.h>
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#define RESET 0x000
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#define RESET_SEL_PLLRESET BIT(12)
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#define RESET_PLLRESET BIT(8)
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#define RESET_SEL_P2RESET BIT(5)
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#define RESET_SEL_P1RESET BIT(4)
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#define RESET_PHYRST_2 BIT(1)
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#define RESET_PHYRST_1 BIT(0)
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#define PHY_RESET_MASK (RESET_PHYRST_1 | RESET_PHYRST_2)
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#define NUM_PORTS 2
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static int rzg2l_usbphy_ctrl_assert(struct reset_ctl *reset_ctl)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
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u32 val;
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val = readl(priv->regs + RESET);
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val |= reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
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/* If both ports are in reset, we can also place the PLL into reset. */
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if ((val & PHY_RESET_MASK) == PHY_RESET_MASK)
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val |= RESET_PLLRESET;
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writel(val, priv->regs + RESET);
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return 0;
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}
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static int rzg2l_usbphy_ctrl_deassert(struct reset_ctl *reset_ctl)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
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u32 val = reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
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/* If either port is out of reset, the PLL must also be out of reset. */
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val |= RESET_PLLRESET;
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clrbits_le32(priv->regs + RESET, val);
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return 0;
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}
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static int rzg2l_usbphy_ctrl_of_xlate(struct reset_ctl *reset_ctl,
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struct ofnode_phandle_args *args)
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{
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if (args->args[0] >= NUM_PORTS)
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return -EINVAL;
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reset_ctl->id = args->args[0];
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return 0;
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}
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struct reset_ops rzg2l_usbphy_ctrl_ops = {
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.rst_assert = rzg2l_usbphy_ctrl_assert,
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.rst_deassert = rzg2l_usbphy_ctrl_deassert,
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.of_xlate = rzg2l_usbphy_ctrl_of_xlate,
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};
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static int rzg2l_usbphy_ctrl_probe(struct udevice *dev)
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{
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struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev);
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struct reset_ctl rst;
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int ret;
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priv->regs = dev_read_addr(dev);
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ret = reset_get_by_index(dev, 0, &rst);
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if (ret < 0) {
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dev_err(dev, "failed to get reset line: %d\n", ret);
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return ret;
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}
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ret = reset_deassert(&rst);
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if (ret < 0) {
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dev_err(dev, "failed to de-assert reset line: %d\n", ret);
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return ret;
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}
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/* put pll and phy into reset state */
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setbits_le32(priv->regs + RESET,
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RESET_SEL_PLLRESET | RESET_PLLRESET |
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RESET_SEL_P1RESET | RESET_PHYRST_1 |
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RESET_SEL_P2RESET | RESET_PHYRST_2);
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return 0;
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}
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static const struct udevice_id rzg2l_usbphy_ctrl_ids[] = {
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{ .compatible = "renesas,rzg2l-usbphy-ctrl", },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(rzg2l_usbphy_ctrl) = {
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.name = "rzg2l_usbphy_ctrl",
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.id = UCLASS_RESET,
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.of_match = rzg2l_usbphy_ctrl_ids,
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.probe = rzg2l_usbphy_ctrl_probe,
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.ops = &rzg2l_usbphy_ctrl_ops,
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.priv_auto = sizeof(struct rzg2l_usbphy_ctrl_priv),
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};
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