Haiying Wang 1f293b417a Add debug information for DDR controller registers ...

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>

2008-10-18 21:54:05 +02:00

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common_timing_params.h

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ctrl_regs.c

Add debug information for DDR controller registers

2008-10-18 21:54:05 +02:00

ddr1_dimm_params.c

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ddr2_dimm_params.c

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ddr.h

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lc_common_dimm_params.c

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main.c

Check DDR interleaving mode

2008-10-18 21:54:05 +02:00

Makefile

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options.c

Check DDR interleaving mode

2008-10-18 21:54:05 +02:00

util.c

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