Marek Vasut d043ee5b49 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 ...

Fix return values to match the common return value convention.

Signed-off-by: Marek Vasut <marex@denx.de>

2015-08-08 14:14:23 +02:00

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altera

ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4

2015-08-08 14:14:23 +02:00

fsl

drivers/ddr/fsl: Adjust bstopre value

2015-08-03 12:06:38 -07:00

marvell

arm: mvebu: a38x: Use correct PEX register access macros

2015-07-23 10:39:25 +02:00