
This patch adds pwm support for MediaTek MT7987 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
803 lines
20 KiB
Plaintext
803 lines
20 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/clock/mediatek,mt7987-clk.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
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/ {
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compatible = "mediatek,mt7987";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clkxtal: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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};
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vproc: regulator-vproc {
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compatible = "regulator-fixed";
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regulator-name = "proc";
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regulator-min-microvolt = <8500000>;
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regulator-max-microvolt = <8500000>;
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regulator-boot-on;
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regulator-always-on;
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};
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firmware {
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optee {
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method = "smc";
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compatible = "linaro,optee-tz";
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status = "okay";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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reg = <0x0>;
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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<&topckgen CLK_TOP_CB_CKSQ_40M>,
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<&apmixedsys CLK_APMIXED_ARM_LL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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reg = <0x1>;
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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<&topckgen CLK_TOP_CB_CKSQ_40M>,
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<&apmixedsys CLK_APMIXED_ARM_LL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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reg = <0x2>;
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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<&topckgen CLK_TOP_CB_CKSQ_40M>,
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<&apmixedsys CLK_APMIXED_ARM_LL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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reg = <0x3>;
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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<&topckgen CLK_TOP_CB_CKSQ_40M>,
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<&apmixedsys CLK_APMIXED_ARM_LL>;
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clock-names = "cpu", "intermediate", "armpll";
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operating-points-v2 = <&cluster0_opp>;
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <850000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <850000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <1600000000>;
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opp-microvolt = <850000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <2000000000>;
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opp-microvolt = <850000>;
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};
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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clk40m: clk40m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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};
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clkitg: clkitg {
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compatible = "simple-bus";
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status = "disabled";
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};
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clksys: soc_clksys {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7987-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7987-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: apmixedsys@1001e000 {
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compatible = "mediatek,mt7987-apmixedsys", "syscon";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7987-sgmiisys",
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"mediatek,mt7987-sgmiisys_0",
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"syscon";
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reg = <0 0x10060000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7987-sgmiisys",
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"mediatek,mt7987-sgmiisys_1",
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"syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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mcusys: mcusys@10400000 {
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compatible = "mediatek,mt7987-mcusys", "syscon";
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reg = <0 0x10400000 0 0x1000>;
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#clock-cells = <1>;
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};
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7987-ethdma",
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"mediatek,mt7987-ethsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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ethsysrst: reset-controller {
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compatible = "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits =
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<0x34 4 0x34 4 0x34 4
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(ASSERT_SET | DEASSERT_CLEAR |
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STATUS_SET)>;
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};
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};
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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cooling-levels = <0 128 255>;
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#cooling-cells = <2>;
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#thermal-sensor-cells = <1>;
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status = "disabled";
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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wmcpu_emi: wmcpu-reserved@50000000 {
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compatible = "mediatek,wmcpu-reserved";
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no-map;
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reg = <0 0x50000000 0 0x00100000>;
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};
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};
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thermal-zones {
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thermal_zone0: soc_thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&lvts 0>;
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trips {
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cpu_trip_crit: crit {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_trip_hot: hot {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_trip_active1: active1 {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_active0: active0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_passive: passive {
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temperature = <40000>;
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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cpu-active-high {
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cooling-device = <&fan 2 2>;
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trip = <&cpu_trip_active1>;
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};
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cpu-active-low {
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cooling-device = <&fan 1 1>;
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trip = <&cpu_trip_active0>;
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};
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cpu-passive {
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cooling-device = <&fan 0 0>;
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trip = <&cpu_trip_passive>;
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};
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};
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};
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thermal_zone1: mcusys_thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&lvts 1>;
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};
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thermal_zone2: eth2p5g_thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&lvts 2>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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hwver: hwver@8000000 {
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compatible = "mediatek,hwver", "syscon";
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reg = <0 0x8000000 0 0x1000>;
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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infra_bus_prot: infra_bus_prot@1000310c {
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compatible = "mediatek,infracfg_ao_bus_hang_prot";
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reg = <0 0x1000310c 0 0x14>;
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status = "disabled";
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7622-wdt",
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"mediatek,mt6589-wdt",
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"syscon";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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status = "disabled";
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};
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7987-pinctrl";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11d00000 0 0x1000>,
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<0 0x11e00000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f40000 0 0x1000>,
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<0 0x11f60000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1",
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"iocfg_rt2", "iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 50>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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pcie1pereset {
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gpio-hog;
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gpios = <36 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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};
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boottrap: boottrap@1001f6f0 {
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compatible = "mediatek,boottrap";
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reg = <0 0x1001f6f0 0 0x20>;
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status = "disabled";
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};
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trng: trng@1020f000 {
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compatible = "mediatek,mt7987-rng";
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status = "disabled";
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7987-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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status = "disabled";
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};
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uart0: serial@11000000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11000000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_52M_UART0_CK>,
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<&infracfg CLK_INFRA_66M_UART0_PCK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART0_SEL>;
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assigned-clock-parents = <&topckgen
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CLK_TOP_CB_CKSQ_40M>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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uart1: serial@11000100 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11000100 0 0x100>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_52M_UART1_CK>,
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<&infracfg CLK_INFRA_66M_UART1_PCK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART1_SEL>;
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assigned-clock-parents = <&topckgen
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CLK_TOP_CB_CKSQ_40M>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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uart2: serial@11000200 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11000200 0 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_52M_UART2_CK>,
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<&infracfg CLK_INFRA_66M_UART2_PCK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART2_SEL>;
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assigned-clock-parents = <&topckgen
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CLK_TOP_CB_CKSQ_40M>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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i2c0: i2c@11003000 {
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compatible = "mediatek,mt7988-i2c",
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"mediatek,mt7981-i2c";
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reg = <0 0x11003000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@11007800 {
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compatible = "mediatek,ipm-spi-quad",
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"mediatek,spi-ipm";
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reg = <0 0x11007800 0 0x100>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_104M_SPI0>,
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<&infracfg CLK_INFRA_66M_SPI0_HCK>;
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assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_MUX_SPI0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>;
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clock-names = "parent-clk", "sel-clk", "spi-clk",
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"hclk";
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status = "disabled";
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};
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spi1: spi@11008800 {
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compatible = "mediatek,ipm-spi-single",
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"mediatek,spi-ipm";
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reg = <0 0x11008800 0 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg CLK_INFRA_104M_SPI1>,
|
|
<&infracfg CLK_INFRA_66M_SPI1_HCK>;
|
|
assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
|
|
<&infracfg CLK_INFRA_MUX_SPI1_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
|
|
<&topckgen
|
|
CLK_TOP_SPIM_MST_SEL>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
|
"hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@11009800 {
|
|
compatible = "mediatek,ipm-spi-quad",
|
|
"mediatek,spi-ipm";
|
|
reg = <0 0x11009800 0 0x100>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg CLK_INFRA_104M_SPI2_BCK>,
|
|
<&infracfg CLK_INFRA_66M_SPI2_HCK>;
|
|
assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg
|
|
CLK_INFRA_MUX_SPI2_BCK_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
|
"hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
lvts: lvts@1100a000 {
|
|
compatible = "mediatek,mt7987-lvts";
|
|
#thermal-sensor-cells = <1>;
|
|
reg = <0 0x1100a000 0 0x1000>;
|
|
clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
|
|
clock-names = "lvts_clk";
|
|
nvmem-cells = <&lvts_calibration>;
|
|
nvmem-cell-names = "e_data1";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbtphy: usb-phy@11c50000 {
|
|
compatible = "mediatek,mt7987",
|
|
"mediatek,generic-tphy-v2";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
tphyu2port0: usb-phy@11c50000 {
|
|
reg = <0 0x11c50000 0 0x700>;
|
|
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
|
|
auto_load_valid;
|
|
nvmem-cells = <&u2_intr_p0>,
|
|
<&u2_auto_load_valid_p0>;
|
|
nvmem-cell-names = "intr", "auto_load_valid";
|
|
};
|
|
|
|
tphyu3port0: usb-phy@11c50700 {
|
|
reg = <0 0x11c50700 0 0x900>;
|
|
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
|
|
auto_load_valid;
|
|
nvmem-cells = <&comb_intr_p0>,
|
|
<&comb_rx_imp_p0>,
|
|
<&comb_tx_imp_p0>,
|
|
<&comb_auto_load_valid>;
|
|
nvmem-cell-names = "intr", "rx_imp", "tx_imp",
|
|
"auto_load_valid";
|
|
|
|
/* MT7987: 4'b0010 default USB30
|
|
* Don't change the '0'
|
|
*/
|
|
mediatek,syscon-type = <&topmisc 0x218 0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
xhci: xhci@11200000 {
|
|
compatible = "mediatek,mt7987-xhci",
|
|
"mediatek,mtk-xhci";
|
|
reg = <0 0x11200000 0 0x2e00>,
|
|
<0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
usb2-lpm-disable;
|
|
status = "disabled";
|
|
};
|
|
|
|
afe: audio-controller@11210000 {
|
|
compatible = "mediatek,mt79xx-audio";
|
|
reg = <0 0x11210000 0 0x9000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
|
|
<&infracfg CLK_INFRA_AUD_26M>,
|
|
<&infracfg CLK_INFRA_AUD_L>,
|
|
<&infracfg CLK_INFRA_AUD_AUD>,
|
|
<&infracfg CLK_INFRA_AUD_EG2>,
|
|
<&topckgen CLK_TOP_AUD_SEL>,
|
|
<&topckgen CLK_TOP_AUD_I2S_M>;
|
|
clock-names = "aud_bus_ck",
|
|
"aud_26m_ck",
|
|
"aud_l_ck",
|
|
"aud_aud_ck",
|
|
"aud_eg2_ck",
|
|
"aud_sel",
|
|
"aud_i2s_m";
|
|
assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
|
<&topckgen CLK_TOP_A1SYS_SEL>,
|
|
<&topckgen CLK_TOP_AUD_L_SEL>,
|
|
<&topckgen CLK_TOP_A_TUNER_SEL>;
|
|
assigned-clock-parents = <&apmixedsys
|
|
CLK_APMIXED_APLL2>,
|
|
<&topckgen
|
|
CLK_TOP_CB_APLL2_D4>,
|
|
<&apmixedsys
|
|
CLK_APMIXED_APLL2>,
|
|
<&topckgen
|
|
CLK_TOP_CB_APLL2_D4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "mediatek,mt7986-mmc";
|
|
reg = <0 0x11230000 0 0x1000>,
|
|
<0 0x11f50000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_EMMC_200M_SEL>,
|
|
<&infracfg CLK_INFRA_MSDC400>,
|
|
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
|
|
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
|
<&infracfg CLK_INFRA_MSDC200_SRC>,
|
|
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
|
|
clock-names = "source", "bus_clk", "axi_cg", "hclk",
|
|
"source_cg", "ahb_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
wed: wed {
|
|
compatible = "mediatek,wed";
|
|
wed_num = <1>;
|
|
};
|
|
|
|
wed0: wed0@15010000 {
|
|
compatible = "mediatek,wed0";
|
|
/* add this property for wed get the pci slot number */
|
|
pci_slot_map = <0>;
|
|
reg = <0 0x15010000 0 0x2000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
wdma: wdma@15104800 {
|
|
compatible = "mediatek,wed-wdma";
|
|
reg = <0 0x15104800 0 0x400>;
|
|
};
|
|
|
|
pcie0: pcie@11280000 {
|
|
compatible = "mediatek,mt7988-pcie",
|
|
"mediatek,mt7987-pcie",
|
|
"mediatek,mt7986-pcie";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11280000 0 0x2000>;
|
|
reg-names = "pcie-mac";
|
|
linux,pci-domain = <0>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0x00 0x20000000 0x00
|
|
0x20000000 0x00 0x00200000>,
|
|
<0x82000000 0x00 0x20200000 0x00
|
|
0x20200000 0x00 0x0fe00000>;
|
|
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
|
|
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
|
|
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
|
|
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
|
|
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
|
"top_133m";
|
|
status = "disabled";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
|
|
<0 0 0 2 &pcie_intc2 1>,
|
|
<0 0 0 3 &pcie_intc2 2>,
|
|
<0 0 0 4 &pcie_intc2 3>;
|
|
pcie_intc2: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@11290000 {
|
|
compatible = "mediatek,mt7988-pcie",
|
|
"mediatek,mt7987-pcie",
|
|
"mediatek,mt7986-pcie";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11290000 0 0x2000>;
|
|
reg-names = "pcie-mac";
|
|
linux,pci-domain = <1>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0x00 0x30000000 0x00
|
|
0x30000000 0x00 0x00200000>,
|
|
<0x82000000 0x00 0x30200000 0x00
|
|
0x30200000 0x00 0x0fe00000>;
|
|
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
|
|
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
|
|
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
|
|
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
|
|
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
|
"top_133m";
|
|
status = "disabled";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
|
<0 0 0 2 &pcie_intc1 1>,
|
|
<0 0 0 3 &pcie_intc1 2>,
|
|
<0 0 0 4 &pcie_intc1 3>;
|
|
pcie_intc1: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
slot1: pcie@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
};
|
|
};
|
|
|
|
topmisc: topmisc@10021000 {
|
|
compatible = "mediatek,mt7987-topmisc", "syscon",
|
|
"mediatek,mt7987-power-controller";
|
|
reg = <0 0x10021000 0 0x10000>;
|
|
#clock-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
/* power domain of the SoC */
|
|
/* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 {
|
|
* reg = <MT7988_POWER_DOMAIN_ETH2P5>;
|
|
* #power-domain-cells = <0>;
|
|
* };
|
|
*/
|
|
};
|
|
|
|
efuse: efuse@11d30000 {
|
|
compatible = "mediatek,efuse";
|
|
reg = <0 0x11d30000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
lvts_calibration: calib@918 {
|
|
reg = <0x918 0x10>;
|
|
};
|
|
|
|
comb_auto_load_valid: usb3-alv-imp@8ee {
|
|
reg = <0x8ee 1>;
|
|
bits = <0 1>;
|
|
};
|
|
|
|
comb_rx_imp_p0: usb3-rx-imp@8ec {
|
|
reg = <0x8ec 1>;
|
|
bits = <0 5>;
|
|
};
|
|
|
|
comb_tx_imp_p0: usb3-tx-imp@8ec {
|
|
reg = <0x8ec 2>;
|
|
bits = <5 5>;
|
|
};
|
|
|
|
comb_intr_p0: usb3-intr@8ec {
|
|
reg = <0x8ec 2>;
|
|
bits = <10 6>;
|
|
};
|
|
|
|
u2_auto_load_valid_p0: usb2-alv-p0@8cc {
|
|
reg = <0x8cc 1>;
|
|
bits = <0 1>;
|
|
};
|
|
|
|
u2_intr_p0: usb2-intr-p0@8cc {
|
|
reg = <0x8cc 1>;
|
|
bits = <1 5>;
|
|
};
|
|
};
|
|
|
|
devapc: devapc@1a110000 {
|
|
compatible = "mediatek,mt7987-devapc";
|
|
reg = <0 0x1a110000 0 0x1000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
netsys: soc_netsys {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
};
|
|
};
|