
The GPIO banks are added as sub nodes or child nodes under the pinctrl node (as per Linux ABI) and the reg property which points to an array of controllers physical base address is removed to align with the Linux devicetree. Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com> Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
309 lines
8.1 KiB
Plaintext
309 lines
8.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/at91.h>
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/{
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model = "Microchip SAM9X60 SoC";
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compatible = "microchip,sam9x60";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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spi0 = &qspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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ARM9260_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
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clock-names = "cpu", "master", "xtal";
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};
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};
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clocks {
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slow_rc_osc: slow_rc_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <18500>;
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb1: usb@600000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00600000 0x100000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: usb@700000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00700000 0x100000>;
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clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>;
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clock-names = "usb_clk", "ehci_clk";
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assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
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assigned-clock-rates = <480000000>;
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status = "disabled";
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};
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ebi: ebi@10000000 {
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compatible = "microchip,sam9x60-ebi";
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#address-cells = <2>;
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#size-cells = <1>;
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atmel,smc = <&smc>;
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microchip,sfr = <&sfr>;
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reg = <0x10000000 0x60000000>;
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ranges = <0x0 0x0 0x10000000 0x10000000
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0x1 0x0 0x20000000 0x10000000
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0x2 0x0 0x30000000 0x10000000
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0x3 0x0 0x40000000 0x10000000
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0x4 0x0 0x50000000 0x10000000
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0x5 0x0 0x60000000 0x10000000>;
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clocks = <&pmc PMC_TYPE_CORE 11>;
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status = "disabled";
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nand_controller: nand-controller {
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compatible = "microchip,sam9x60-nand-controller";
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ecc-engine = <&pmecc>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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};
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};
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sdhci0: sdhci-host@80000000 {
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compatible = "microchip,sam9x60-sdhci";
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reg = <0x80000000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
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assigned-clock-rates = <100000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
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bus-width = <4>;
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};
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sdhci1: sdhci-host@90000000 {
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compatible = "microchip,sam9x60-sdhci";
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reg = <0x90000000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
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assigned-clock-rates = <100000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
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bus-width = <4>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qspi: spi@f0014000 {
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compatible = "microchip,sam9x60-qspi";
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reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
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clock-names = "pclk", "qspick";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pit64b0: timer@f0028000 {
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compatible = "microchip,sam9x60-pit64b";
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reg = <0xf0028000 0xec>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
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clock-names = "pclk", "gclk";
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};
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flx0: flexcom@f801c600 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xf801c000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xf801c000 0x800>;
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status = "disabled";
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};
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macb0: ethernet@f802c000 {
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compatible = "cdns,sam9x60-macb", "cdns,macb";
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reg = <0xf802c000 0x100>;
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clock-names = "hclk", "pclk";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
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status = "disabled";
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};
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sfr: sfr@f8050000 {
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compatible = "microchip,sam9x60-sfr", "syscon";
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reg = <0xf8050000 0x100>;
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};
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pmecc: ecc-engine@ffffe000 {
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compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
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reg = <0xffffe000 0x300>,
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<0xffffe600 0x100>;
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};
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smc: smc@ffffea00 {
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compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
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reg = <0xffffea00 0x100>;
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};
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aic: interrupt-controller@fffff100 {
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compatible = "microchip,sam9x60-aic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xfffff100 0x100>;
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atmel,external-irqs = <31>;
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
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clock-names = "usart";
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};
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pinctrl: pinctrl@fffff400 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
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ranges = <0xfffff400 0xfffff400 0x800>;
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/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
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atmel,mux-mask = <
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/* A B C */
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0xffffffff 0xffe03fff 0xef00019d /* pioA */
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0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
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0xffffffff 0xffffffff 0xf83fffff /* pioC */
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0x003fffff 0x003f8000 0x00000000 /* pioD */
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>;
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pioA: gpio@fffff400 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x200>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
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};
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pioB: gpio@fffff600 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff600 0x200>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
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#gpio-cells = <2>;
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gpio-controller;
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#gpio-lines = <26>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
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};
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pioC: gpio@fffff800 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff800 0x200>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
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};
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pioD: gpio@fffffa00 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffffa00 0x200>;
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interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
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#gpio-cells = <2>;
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gpio-controller;
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#gpio-lines = <22>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
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};
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};
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pmc: pmc@fffffc00 {
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compatible = "microchip,sam9x60-pmc";
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reg = <0xfffffc00 0x200>;
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#clock-cells = <2>;
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clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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status = "okay";
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};
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reset_controller: rstc@fffffe00 {
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compatible = "microchip,sam9x60-rstc";
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reg = <0xfffffe00 0x10>;
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clocks = <&clk32 0>;
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};
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pit: timer@fffffe40 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe40 0x10>;
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clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
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};
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clk32: sckc@fffffe50 {
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compatible = "microchip,sam9x60-sckc";
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reg = <0xfffffe50 0x4>;
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clocks = <&slow_rc_osc>, <&slow_xtal>;
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#clock-cells = <1>;
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};
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};
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};
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onewire_tm: onewire {
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compatible = "w1-gpio";
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status = "disabled";
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};
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};
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