blog: home logic: more explicitly break down the inverter chain diagrams
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@ -239,20 +239,26 @@ just take our clocked inverter, build 3 of these, and wire them in series, right
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but it's not that simple: we have a few stray signals we need to look closer at first.
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consider the case where all cores are polarized CW (logic '1'). then we apply a positive pulse to
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core S1 in order to force it into the CCW state.
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consider the case where all cores are polarized CW (logic '1'), below
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(the circular arrows in the center of each core indicates its polarization).
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as S1 transitions from CW to CCW polarization, it dumps current onto the wire connecting it to S2,
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successfully transferring the logic '1' into an inverted logic '0' stored into S2.
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but it _also_ dumps a pulse into the wire connecting S1 to S0, clearing it too!
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after applying the pulse to S1, _all_ the cores end up polarized CCW:
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then we apply a positive pulse to core S1 in order to force it into the CCW state:
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as S1 transitions from CW to CCW polarization, it dumps current as shown onto the wires connected to it.
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after some time, this polarizes the neighboring cores.
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we successfully transferred data from S1 to S2, but in the process, destroyed whatever other state was in S0!
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it's actually worse than that. imagine another core after S2.
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when S2 changes state, it'll dump current onto its output too, and effect things downstream of _it_.
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when S2 changes state during this sequence, it'll dump current onto its output too,
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and thereby effect things downstream of _it_.
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in this naive inverter chain, a transition _anywhere_ can force an arbitrary number of downstream
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or upstream cores into the '0' state.
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@ -263,6 +269,24 @@ and therefore nothing downstream of it would be effected by S1's transition.
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this hints that we can isolate data transfers by inserting buffer cores into this chain
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which are fixed at the '0' state during the CTL1 transition.
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TODO: 4 element inverter, with the two edges being held low.
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for brevity i replaced the visual polarizations with their logic values.
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finally, we can tile this group of four cores to construct inverter chains of arbitrary length
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TODO: 8 element inverter chain. show four clock cycles: from data arriving into the element, to data leaving it.
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in effect, this is a chain of _two_ inverters,
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where each inverter has four clock cycles of latency.
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if we were to add an additional input winding to the first core in a group,
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then that group would now serve as a NOR gate.
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so we've got a framework for cascading, synchronous logic: use this four-core device
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as our primitive logic gate and arrange it into whatever circuit we want.
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the control signals are nastier than with CMOS, but the concept's there.
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## TODO: show illustrations of clocked logic, buffered, with a gain stage
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- include simulation results of the gain stage
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@ -0,0 +1,628 @@
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After Width: | Height: | Size: 30 KiB |
|
Before Width: | Height: | Size: 29 KiB After Width: | Height: | Size: 29 KiB |
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Reference in New Issue