blog: coremem: logic gates background

content/blog/DRAFT-2022-05-26-home-built-computation/index.md

@@ -148,11 +148,34 @@ and then monitor the voltage across the sense wire (purple line), loaded with a
 there's always some residual output onto the sense wire -- via inductance from the drive wire if nothing else --
 but the output during a 1 -> 0 state transition (top plot) shows substantially more energy than the 0 -> 0 case (bottom plot).
 
-if we were using these as memory in a core memory array, we could place a capacitor across the sense wire, connect that to a comparator (opamp),
-and recover a clean binary signal from this.
+if we wanted to recover a binary signal from this, we could place a capacitor across the sense wire, connect that to a comparator (opamp),
+and observe a clean logic-high or logic-low voltage at the output.
 
-## TODO: show illustrations of basic logic gates
-- include simulation results
+## Logic Gates
+
+in the 60's, one would wire hundreds or thousands of these ferrite cores into a grid, like this:
+
+![](core-memory-array.jpg)
+
+(photo from [Konstantin Lanzet](https://en.wikipedia.org/wiki/File:KL_Kernspeicher_Makro_1.jpg))
+
+3 wires are routed through each core:
+- a green wire runs through each core along a specific _row_ (6 of these wires are pictured).
+- a red wire runs through each core along a given _column_ (9 of these wires are pictured).
+- and the diagonal red wire runs through _every core in the array_.
+
+the diagonal wire serves the role of the sense wire in our earlier example. we wrapped our wires around the core
+but you can actually just route them _through_ the core to achieve the same thing, just with lower fidelity.
+
+the 6 green and 8 red wires serve the role of _row select_ and _column select_, respectively.
+by driving a specific row and a specific column _simultaneously_, exactly 1 of these 48 cores would be written.
+the drive currents are calibrated such that the field from any _one_ of these signals would lie somewhere
+in the inactive region of our M-H curve from earlier, but the fields from _both_ of the signals added together
+would be enough to move the core substantially along this curve.
+
+in this way, these core memories from the 60's were already performing 'AND' operations. 
+
+TODO: show a majority gate
 
 ## TODO: show illustrations of clocked logic, with output buffers