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blog: home logic: prepare the stage for simulation results

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colin 2022-07-15 15:04:54 -07:00
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content/blog/DRAFT-2022-05-26-home-built-computation/index.md
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@ -344,8 +344,27 @@ so we've got a framework for cascading, synchronous logic: use this four-core de
as our primitive logic gate and arrange it into whatever circuit we want.
the control signals are nastier than with CMOS, but the concept's there.
## Validation
## TODO: discuss simulation, show results
one can buy ferrite cores and breadboard these designs.
but it's messy and iterations are costly.
instead, we can simulate this.
Maxwell's equations govern all of this and are, mathematically, very simple.
correspondingly, the
[Finite-Difference Time-Domain method](https://en.wikipedia.org/wiki/Finite-difference_time-domain_method) (FDTD)
allows one to apply these equations to a discretized grid of space and
solve for the state of that space at a nearby instant in time.
given some initial state (and injecting our control signals) we can iteratively solve
for any instant in time with as little as a hundred-or-so lines of code.
there are whole books and [course material](https://eecs.wsu.edu/~schneidj/ufdtd/ufdtd.pdf)
out there for doing this, and i built a [GPU-capable FDTD library](https://git.uninsane.org/colin/fdtd-coremem)
just for this project.
so here's some simulation results from our 4-core inverter above:
TODO: simulation
## TODO: discuss gain stage