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blog: home logic: plan how to correct the parity on these buffers. 

this is not easy to explain well.
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colin 2022-07-12 18:30:52 -07:00
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33
content/blog/DRAFT-2022-05-26-home-built-computation/index.md
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@ -117,6 +117,8 @@ apply a positive field again, and M won't change much.
apply a negative field, and M will repeat the process in reverse, settling at the star instead.
crucially, applying a _small_ negative field won't change M much, so the data storage is resilient to some amount of noise.
TODO: need to explain somewhere that "square-loop" is what we want -- most importantly, the thresholding allows us to amplify partially polarized states to a fully polarized state, giving us well-defined logic levels.
## Reading and Writing Bits
![](minimal-magnetic-core.jpeg)
@ -269,25 +271,42 @@ and therefore nothing downstream of it would be effected by S1's transition.
this hints that we can isolate data transfers by inserting buffer cores into this chain
which are fixed at the '0' state during the CTL1 transition.
![](buffered-inverter-stage.svg)
![TODO: add CTL2 0V signal; CTL0 and CTL3 should be +Vdd instead of negative; make the buffer cores be non-inverting](buffered-inverter-stage.svg)
for brevity i replaced the visual polarizations with their logic values
and whatever way they're transitioning. note that current still _flows_ into the buffers,
it just doesn't do anything. crucially, not current flows out the other end of the buffers.
it just doesn't do anything. crucially, no current flows out the other end of the buffers.
we keep the two buffer cores at '0' by driving them with a negative voltage.
we keep the two buffer cores (CTL0 and CTL3) at '0' by driving them with a negative voltage.
not strictly necessary, but the real circuit experiences things like reflections
which would otherwise nudge the buffers away from their set point.
finally, we can tile this group of four cores to construct inverter chains of arbitrary length
finally, we can tile this group of four cores to construct inverter chains of arbitrary length:
![](staged-inverter-chain.svg)
note that i've annotated only two of the cores as having a state:
each of these two "inverters" carries only one bit, with the rest of the cores being used as buffers.
as we mess with the control signal, that state will propagate downstream and eventually leave the inverter.
each of these two outlined "inverters" carries only one bit, with the rest of the cores being used as buffers.
you might think that when we cascade these devices, we could remove the input buffer of the second
device because it's already guarded by the output buffer of the first device.
unfortunately, that's not the case: i showed that buffer cores are needed when we discharge the inverter,
but after we discharge it we need to charge it _back_ to logic '1', and this requires an additional buffer.
but this does present a problem: each stage of this chain performs 4 inversions -- so it's no longer
an inverter chain, but rather a shift register. we can solve this by inverting the wiring on 3 of these
cores, and leaving just one inverting core:
<!-- there are other ways, too. we can have a 3-clock device if we switch to
differential signals: +Vdd for logic '1' and -Vdd for logic '0'. but this requires either
6 cores per device, or three more-difficult-to-manufacture '8'-shaped cores -->
![TODO](buffered-inverter-stage-correct-parity.svg)
as data arrives into this device, it's immediately inverted, and will later be propagated downstream.
if we're deliberate with our control signals, we can cascade these inverter devices without issue.
here's what that looks like over time:
TODO: show four clock cycles: from data arriving into the element, to data leaving it.
TODO: VALIDATE THAT WE ACTUALLY NEED FOUR CORES. am i sure we don't need only 3?
TODO: need to switch one of these inverters into a strict buffer stage.
in effect, this is a chain of _two_ inverters,
where each inverter has four clock cycles of latency.

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content/blog/DRAFT-2022-05-26-home-built-computation/staged-inverter-chain.svg
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