app: multi_core_inverter: drive all four cores for four clock cycles
This commit is contained in:
@@ -52,7 +52,7 @@ type Backend = spirv::WgpuBackend;
|
||||
|
||||
fn main() {
|
||||
coremem::init_logging();
|
||||
coremem::init_debug();
|
||||
// coremem::init_debug();
|
||||
let um = |n| n as f32 * 1e-6;
|
||||
// let ns = |n| n as f32 * 1e-9;
|
||||
let ps = |n| n as f32 * 1e-12;
|
||||
@@ -146,16 +146,19 @@ fn main() {
|
||||
// 0, +Vdd, +Vdd, +Vdd
|
||||
// TODO: this is wrong (as is the diagram in the blog)! CTL0, being an inverter,
|
||||
// needs -Vdd to recharge to +polarization
|
||||
let cycles = 1;
|
||||
let cycles = 4;
|
||||
let duration = Seconds(clock_phase_duration * (cycles + 2) as f32);
|
||||
// each row N denotes the drive currents at clock cycle N.
|
||||
// each col M denotes the drive current at core M.
|
||||
let drive_map = [
|
||||
[1, 0, 1, 1],
|
||||
[1, 1, 0, 1],
|
||||
[1, 1, 1, 0],
|
||||
[0, 1, 1, 1i32],
|
||||
];
|
||||
for cycle in 0..cycles {
|
||||
for core in 0..1 { // TODO: core 0
|
||||
let dir = 1;
|
||||
//let dir = if (cycle+core) % 4 == 0 {
|
||||
// 0
|
||||
//} else {
|
||||
// 1
|
||||
//};
|
||||
for core in 0..4 {
|
||||
let dir = drive_map[cycle as usize][core as usize];
|
||||
if dir != 0 {
|
||||
// micro opt/safety: don't place zero-magnitude stimuli
|
||||
driver.add_stimulus(input(&ctl(core), cycle, dir));
|
||||
@@ -163,7 +166,7 @@ fn main() {
|
||||
}
|
||||
}
|
||||
|
||||
let prefix = "out/applications/multi_core_inverter/2/";
|
||||
let prefix = "out/applications/multi_core_inverter/4/";
|
||||
let _ = std::fs::create_dir_all(&prefix);
|
||||
// driver.add_state_file(&*format!("{}state.bc", prefix), 9600);
|
||||
driver.add_serializer_renderer(&*format!("{}frame-", prefix), 400, None);
|
||||
|
Reference in New Issue
Block a user