multi_core_inverter: add the ctl wire loop

This commit is contained in:
2022-07-15 21:53:34 -07:00
parent 0d199445f1
commit 6c63c7dc7d

View File

@@ -32,7 +32,7 @@
use coremem::geom::{Meters, Torus};
use coremem::sim::units::Seconds;
use coremem::mat::Ferroxcube3R1MH;
use coremem::mat::{Ferroxcube3R1MH, IsomorphicConductor};
use coremem::spirv;
use coremem::{Driver, SpirvDriver};
@@ -45,6 +45,8 @@ fn main() {
let feat_size = um(10);
let s_major = um(160);
let s_minor = um(30);
let ctl_major = um(80);
let ctl_minor = um(30);
let s0x = um(400);
let sy = um(400);
@@ -55,14 +57,17 @@ fn main() {
let duration = Seconds(ns(1));
let s0 = Torus::new_xy(Meters::new(s0x, sy, sz), s_major, s_minor);
let ctl0 = Torus::new_yz(Meters::new(s0x, sy + s_major, sz), ctl_major, ctl_minor);
let ferro_mat = Ferroxcube3R1MH::new();
let wire_mat = IsomorphicConductor::new(1e6);
let mut driver: SpirvDriver<Mat> = Driver::new_spirv(sim_bounds, feat_size);
driver.add_classical_boundary(sim_padding);
driver.fill_region(&s0, ferro_mat);
driver.fill_region(&ctl0, wire_mat);
let prefix = "out/applications/multi_core_inverter/";
let prefix = "out/applications/multi_core_inverter/2/";
let _ = std::fs::create_dir_all(&prefix);
driver.add_state_file(&*format!("{}state.bc", prefix), 9600);
driver.add_serializer_renderer(&*format!("{}frame-", prefix), 36000, None);