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app: multi-core-inverter: explore multiple parameterizations in one run

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colin
2022-08-24 02:08:06 -07:00
parent 488d0fe62a
commit 6d717fdda4
1 changed files with 68 additions and 10 deletions
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78
crates/applications/multi_core_inverter/src/main.rs
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@@ -165,6 +165,19 @@ impl Params {
.gated(R::zero(), self.clock_phase_duration.cast())
.shifted(start.cast())
}
fn with_input_magnitude(mut self, p: f32) -> Self {
self.input_magnitude = p;
self
}
fn with_clock_phase_duration(mut self, p: f32) -> Self {
self.clock_phase_duration = p;
self
}
fn with_clock_decay(mut self, p: f32) -> Self {
self.clock_decay = p;
self
}
}
/// 5 cores in sequence; analyze how they propagate a *specific* input signal
@@ -253,17 +266,14 @@ fn drive_map_isolated_inv_square() -> [[ClockState; 2]; 6] {
]
}
fn main() {
coremem::init_logging();
// coremem::init_debug();
// let ns = |n| n as f32 * 1e-9;
let feat_size = um(10);
let params = Params {
input_magnitude: 2.0e7,
clock_phase_duration: ps(160000),
clock_decay: ps(12000),
input_magnitude: 0.0,
clock_phase_duration: 0.0,
clock_decay: 0.0,
// 's' = core (ferromagnetic part)
s_major: um(160),
s_minor: um(30),
@@ -276,6 +286,57 @@ fn main() {
sy: um(400),
sz: um(280),
};
// let drive_map = drive_map_5_core_inv(ClockState::HoldLow, ClockState::ReleaseLow);
// let drive_map = drive_map_isolated_inv();
// let drive_map = drive_map_isolated_inv_square();
run_sim(
"32-160ns-12000ps-2e7A/",
drive_map_isolated_inv(),
params
.with_clock_phase_duration(ps(160000))
.with_clock_decay(ps(12000))
.with_input_magnitude(2.0e7)
);
run_sim(
"33-160ns-12000ps-1e7A/",
drive_map_isolated_inv(),
params
.with_clock_phase_duration(ps(160000))
.with_clock_decay(ps(12000))
.with_input_magnitude(1.0e7)
);
run_sim(
"34-320ns-12000ps-1e7A/",
drive_map_isolated_inv(),
params
.with_clock_phase_duration(ps(320000))
.with_clock_decay(ps(12000))
.with_input_magnitude(1.0e7)
);
run_sim(
"35-320ns-24000ps-1e7A/",
drive_map_isolated_inv(),
params
.with_clock_phase_duration(ps(320000))
.with_clock_decay(ps(24000))
.with_input_magnitude(1.0e7)
);
run_sim(
"36-320ns-12000ps-2e7A/",
drive_map_isolated_inv(),
params
.with_clock_phase_duration(ps(320000))
.with_clock_decay(ps(12000))
.with_input_magnitude(2.0e7)
);
}
fn run_sim<const C: usize, const R: usize>(
name: &str, drive_map: [[ClockState; C]; R], params: Params
) {
// let ns = |n| n as f32 * 1e-9;
let feat_size = um(10);
let sim_bounds = |num_cores| Meters::new(params.sx(num_cores), params.sy * 2.0, params.sz * 2.0);
let sim_padding = Meters::new(um(80), um(80), um(80));
@@ -283,9 +344,6 @@ fn main() {
//////// define the control signals/transitions
// each row N denotes the drive currents at clock cycle N.
// each col M denotes the drive current at core M.
// let drive_map = drive_map_5_core_inv(ClockState::HoldLow, ClockState::ReleaseLow);
let drive_map = drive_map_isolated_inv();
// let drive_map = drive_map_isolated_inv_square();
let num_cycles = drive_map.len() as u32;
let num_cores = drive_map[0].len() as u32;
let mut core_drivers = vec![Vec::default(); num_cores as usize];
@@ -365,7 +423,7 @@ fn main() {
driver.add_stimulus(s);
}
let prefix = "out/applications/multi_core_inverter/32-160ns-12000ps-2e7A/";
let prefix = format!("out/applications/multi_core_inverter/{}/", name);
let _ = std::fs::create_dir_all(&prefix);
driver.add_state_file(&*format!("{}state.bc", prefix), 25600);
// driver.add_serializer_renderer(&*format!("{}frame-", prefix), 6400, None);