app: stacked_cores: new 53-xx run, where we buffer differential signals
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@ -341,8 +341,10 @@ impl Params {
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)
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);
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// how far to bring the wire past the center of the torus circle
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let outside_small = self.s_minor * 2.0;
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let outside_large = self.s_minor * 2.0 + self.coupling_minor * 4.0;
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// self.s_minor * 2.0 works to dodge the core itself,
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// but larger values are required to also dodge direct couplings we might be near to.
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let outside_small = self.s_minor * 4.0;
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let outside_large = self.s_minor * 4.0 + self.coupling_minor * 4.0;
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let outside_top_center_z = self.coupling_major;
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let outside_bot_center_z = -self.coupling_major;
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let bring_outside_top_small = Cube::new(
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@ -1343,6 +1345,20 @@ fn drive_map_or_gate(amp0: f32, amp1: f32) -> [[ClockState; 4]; 4] {
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]
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}
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#[allow(unused)]
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fn drive_map_buf_53(amp0: f32, amp1: f32) -> [[ClockState; 4]; 2] {
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use ClockState as C;
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// amplitudes are inverted from what you would expect.
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// hold(-1) puts the core into a positive M
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[
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// init S1 pos, S2 pos; charge S0 neg, S3 neg
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[C::release_high(), C::release(-amp0), C::release(-amp1), C::release_high()],
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// clear S1 -> S0, S2 -> S3
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[C::float(), C::hold_high(), C::hold_high(), C::float(), ],
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]
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}
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fn asymmetric_inverter_name(p: &Params, sim_id: &str, windings: u32, init_flt: f32) -> String {
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let init_int = (init_flt.abs() * 100.0 + 0.5) as u32;
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let init_level = if init_flt > 0.0 {
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@ -1487,6 +1503,7 @@ fn couple_asymmetric_buffer(params: &Params, sender: u32, loops: u32, slot_offse
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let slots_per_asym = 2*loops;
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// couple c to c+1
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let c1 = c0+1;
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// wires which actually connect c0 to c1
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let mut params = params
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.with_coupling(c0, c1, slot_offset, net_slots, CouplingMethod::direct_half_exterior())
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.with_coupling(c0, c1, slot_offset + slots_per_asym - 1, net_slots, CouplingMethod::direct_half_interior())
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@ -1514,6 +1531,63 @@ fn couple_asymmetric_buffer(params: &Params, sender: u32, loops: u32, slot_offse
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params
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}
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fn couple_asymmetric_buffer_bi(params: &Params, c0: u32, c0_loops: u32, c1_loops: u32, slot_offset: u32, net_slots: u32) -> Params {
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let slots_per_asym = 2*(c0_loops.max(c1_loops));
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// couple c to c+1
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let c1 = c0+1;
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// wires which actually connect c0 to c1
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let mut params = params
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.with_coupling(c0, c1, slot_offset, net_slots, CouplingMethod::direct_half_exterior())
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.with_coupling(c0, c1, slot_offset + slots_per_asym - 1, net_slots, CouplingMethod::direct_half_interior())
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;
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// loops for sender c0
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for i in 0..slots_per_asym {
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if i < 2*c0_loops {
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if i % 2 == 0 {
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// bring up
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params = params.with_coupling(c0, c0, slot_offset + i, net_slots, CouplingMethod::SelfLoopHalfInterior);
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// bring to next slot
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params = params.with_coupling(c0, c0, slot_offset + i, net_slots, CouplingMethod::SelfAngularTop);
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} else {
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// bring down
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params = params.with_coupling(c0, c0, slot_offset + i, net_slots, CouplingMethod::SelfLoopHalfExterior);
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if i + 1 != slots_per_asym {
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// bring to next slot -- if there is one
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params = params.with_coupling(c0, c0, slot_offset + i, net_slots, CouplingMethod::SelfAngularBot);
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}
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}
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} else if i + 1 != slots_per_asym {
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// bring to next slot -- if there is one
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params = params.with_coupling(c0, c0, slot_offset + i, net_slots, CouplingMethod::SelfAngularBot);
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}
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}
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// loops for receiver c1
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for i in 0..slots_per_asym {
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if i < 2*c1_loops {
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if i % 2 == 0 {
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// bring down
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params = params.with_coupling(c1, c1, slot_offset + i, net_slots, CouplingMethod::SelfLoopHalfInterior);
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// bring to next slot
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params = params.with_coupling(c1, c1, slot_offset + i, net_slots, CouplingMethod::SelfAngularBot);
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} else {
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// bring up
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params = params.with_coupling(c1, c1, slot_offset + i, net_slots, CouplingMethod::SelfLoopHalfExterior);
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if i + 1 != slots_per_asym {
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// bring to next slot -- if there is one
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params = params.with_coupling(c1, c1, slot_offset + i, net_slots, CouplingMethod::SelfAngularTop);
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}
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}
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} else if i + 1 != slots_per_asym {
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// bring to next slot -- if there is one
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params = params.with_coupling(c1, c1, slot_offset + i, net_slots, CouplingMethod::SelfAngularTop);
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}
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}
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params
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}
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fn main() {
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coremem::init_logging();
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// coremem::init_debug();
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@ -5680,7 +5754,7 @@ fn main() {
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}
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}
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if true {
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if false {
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for init_set in [
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&[
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// establish domain/range for M0 fixed at -1
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@ -5788,6 +5862,86 @@ fn main() {
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}
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}
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}
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if true {
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for init_set in [
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&[
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// establish rough domain/range
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(-1.00, 1.00),
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(-1.00, -1.00),
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( 0.00, 0.00),
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( 0.20, -0.20),
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( 0.10, -0.10),
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][..],
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&[
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// more detailed sweep
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( 0.30, -0.30),
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( 0.05, -0.05),
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( 0.15, -0.15),
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( 0.25, -0.25),
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][..],
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&[
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// test some asymmetries -- specifically where A1 is higher than expected
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( 0.20, 0.00),
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( 0.20, -0.10),
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( 0.20, 0.10),
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( 0.30, 0.00),
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( 0.30, -0.20),
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( 0.30, -0.10),
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( 0.10, 0.00),
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][..],
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] {
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for (ctl_cond, coupling_cond, clock_duration, clock_decay, coupling_loops, inp_loops, s_major, cur_flt) in [
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// total slot use count is L*(4*A + 1),
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// where L is the "coupling loops" and A is the inp_loops ("asymmetric loops")
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// e.g. L=8, A=1 gives 40
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(2e3, 2e4, ps(2000), ps(100), 8, 1, um(400), 3e10),
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(2e3, 2e4, ps(2000), ps(100), 8, 1, um(400), 2e10),
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] {
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for &(init_flt_a, init_flt_b) in init_set {
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// each core is coupled to 2 others + control slots
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// M1 <-> M2 is symmetric (inputs)
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// M1 -> M0 & M2 -> M3 are asymmetric (tx input -> output)
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// M0 <-> M3 is symmetrics (outputs)
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let slots_per_asym = 2*inp_loops;
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let net_slots = 2*slots_per_asym + 1;
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let mut params = params_v2
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.with_clock_phase_duration(clock_duration)
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.with_clock_decay(clock_decay)
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.with_ctl_conductivity(ctl_cond)
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.with_coupling_conductivity(coupling_cond)
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.with_s_major(s_major)
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.with_coupling_loops(coupling_loops)
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.with_input_magnitude(cur_flt)
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// control loops
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.with_coupling(0, 0, 0, net_slots, CouplingMethod::Control)
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.with_coupling(1, 1, 0, net_slots, CouplingMethod::Control)
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.with_coupling(2, 2, 0, net_slots, CouplingMethod::Control)
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.with_coupling(3, 3, 0, net_slots, CouplingMethod::Control)
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;
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for i in 0..slots_per_asym {
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// couple output core 0 to core 3
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params = params.with_coupling(0, 3, 1+i, net_slots, CouplingMethod::Outside);
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// couple input core 1 to core 2
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params = params.with_coupling(1, 2, 1+i, net_slots, CouplingMethod::Direct);
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}
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// couple input M1 -> output M0
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params = couple_asymmetric_buffer_bi(¶ms, 0 /* low core */, 0, inp_loops, 1 + slots_per_asym /* slot offset */, net_slots);
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// couple input M2 -> output M3
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params = couple_asymmetric_buffer_bi(¶ms, 2 /* low core */, inp_loops, 0, 1 + slots_per_asym /* slot offset */, net_slots);
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let name = asymmetric_binary_gate_name(
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¶ms, "53-buf-", coupling_loops /* ctl loops */, coupling_loops, 2*inp_loops + 1, init_flt_a, init_flt_b
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);
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run_sim(
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&name,
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drive_map_buf_53(init_flt_a, init_flt_b),
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params,
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);
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}
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}
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}
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}
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}
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