add a new crate where i'll explicitly simulate the inverter i hypothesize in an upcoming blog about this project

Cargo.lock

@@ -1241,6 +1241,13 @@ version = "0.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "5474f8732dc7e0635ae9df6595bcd39cd30e3cfe8479850d4fa3e69306c19712"
 
+[[package]]
+name = "multi_core_inverter"
+version = "0.1.0"
+dependencies = [
+ "coremem",
+]
+
 [[package]]
 name = "naga"
 version = "0.8.5"

Cargo.toml

@@ -7,6 +7,7 @@ members = [
     "crates/spirv_backend_runner",
 
     "crates/applications/buffer_proto5",
+    "crates/applications/multi_core_inverter",
     "crates/applications/sr_latch",
     "crates/applications/wavefront",
 ]

crates/applications/multi_core_inverter/Cargo.toml

@@ -0,0 +1,8 @@
+[package]
+name = "multi_core_inverter"
+version = "0.1.0"
+authors = ["Colin <colin@uninsane.org>"]
+edition = "2021"
+
+[dependencies]
+coremem = { path = "../../coremem" }

crates/applications/multi_core_inverter/src/main.rs

@@ -0,0 +1,35 @@
+//! this example demonstrates the type of four-core clocked inverter conceived
+//! of in the https://uninsane.org/ blogpost.
+//!
+//! we're going for something like this:
+//!
+//! ```
+//!          ____         ____         ____         ____
+//!  + ___  /    \ +___  /    \ +___  /    \ +___  /    \  ___ +
+//! IN ___ |o    o| ___ |x    o| ___ |x    o| ___ |x    o| ___ OUT
+//!  -      \_o__/ -     \_o__/ -     \_o__/ -     \_o__/      -
+//!           ||           ||           ||           ||
+//!          +  -         +  -         +  -         +  -
+//!          CTL0         CTL1         CTL2         CTL3
+//! ```
+//!
+//! conventions:
+//! - CW core polarization is logic '1'.
+//! - differential signals are assumed to flow clockwise. i.e. left-to-right, with + on top and -
+//!   on bottom.
+//! - 'x' denotes a signal going "into" the page. 'o' for a signal going "out of" the page.
+//! - the core driven by CTLn is named Sn, interchangeably used to represent the state (0 or 1) of
+//!   that core
+//!
+//! hence:
+//! - the input into core S0 has current flowing out of the page and tends to drive S0 to logic '0'.
+//! - the input into S1, S2, S3 tends these cores to logic '1'.
+//! - a positive current to CTLn will "clear" Sn to the logic '0' state.
+//!
+//! in this device, S0 is effectively an inverter, with S1, S2, S3 acting as buffers.
+//! for the purpose of this simulation, all terminal wires are closed loops either explicitly
+//! driven or measured.
+
+fn main() {
+    println!("Hello, world!");
+}