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app: stacked_cores: fix flipped 41-xx measurements

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This commit is contained in:
colin
2022-10-16 06:02:13 -07:00
parent e8adf6eaa7
commit c458b3135b
4 changed files with 53 additions and 11 deletions
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19
crates/applications/stacked_cores/scripts/inverter_characteristics.py
View File

@@ -42,17 +42,26 @@ class Piecewise:
(s*(x + p), s*(y + p)) for (x, y) in self.xy
])
def logically_inverted(self) -> 'Piecewise':
""" return a Piecewise that evaluates to 1-y """
def inverted_y(self) -> 'Piecewise':
return Piecewise([
(x, 1-y) for (x, y) in self.xy
(x, -y) for (x, y) in self.xy
])
def logically_inverted_x(self) -> 'Piecewise':
def inverted_x(self) -> 'Piecewise':
return Piecewise([
(1-x, y) for (x, y) in self.xy
(-x, y) for (x, y) in self.xy
][::-1])
def inverted_xy(self) -> 'Piecewise':
return self.inverted_x().inverted_y()
def logically_inverted(self) -> 'Piecewise':
""" return a Piecewise that evaluates to 1-y """
return self.inverted_y().shifted_y(1.0)
def logically_inverted_x(self) -> 'Piecewise':
return self.inverted_x().shifted_x(1.0)
def logically_inverted_xy(self) -> 'Piecewise':
return self.logically_inverted_x().logically_inverted()

4
crates/applications/stacked_cores/scripts/plot_inverters.py
View File

@@ -132,7 +132,7 @@ of_interest += [(p, get_meas(p)) for p in
# of_interest += filter_meas(run="40")
of_interest = filter_meas(run="42", wrappings=7)
# of_interest = filter_meas(run="42", wrappings=7)
# of_interest += filter_meas(viable_inverter=True)
# of_interest += filter_meas(rad_um=400, run="41")
# of_interest += filter_meas(run="40", rad_um=800, couplings=18, wrappings=5)
@@ -141,7 +141,7 @@ of_interest = filter_meas(run="42", wrappings=7)
# of_interest += filter_meas(run="42", rad_um=400, couplings=9)
# of_interest += filter_meas(run="42", rad_um=400, couplings=2)
# of_interest += filter_meas(run="42", rad_um=400, couplings=6)
# of_interest += filter_meas(run="43")
of_interest += filter_meas(run="41")
# plot cascaded inverter -> buffer
# for (inv_p, inv_curve) in filter_meas(is_inverter=True):

31
crates/applications/stacked_cores/scripts/stacked_cores_40xx_db.py
View File

@@ -48,6 +48,10 @@ class SimParams:
def is_inverter(self) -> bool:
raise NotImplementedError
@property
def is_discharge_high(self) -> bool:
return False # see 41-xx
@property
def t_last(self) -> float:
return 3e-9
@@ -105,6 +109,12 @@ class SimParams41(SimParams):
def is_inverter(self) -> bool:
return False
@property
def is_discharge_high(self) -> bool:
# 41-xx has the unfortunate case that we encoded the CLEAR operation
# to charge core 0 HIGH, and push core 1 towards LOW on successful transfer
return True
class SimParams42(SimParams):
@property
def run(self) -> str:
@@ -288,7 +298,11 @@ sims = [
(SimParams46(5, 1, 400, "1e10"), None, 20000),
(SimParams46(5, 1, 400, "2e10"), None, 20000),
(SimParams46(5, 1, 400, "4e10"), None, 20000),
(SimParams46(7, 1, 600, "5e9"), None, 20000),
(SimParams46(7, 1, 600, "8e9"), None, 20000),
(SimParams46(7, 1, 600, "1e10"), None, 20000),
(SimParams46(7, 1, 600, "2e10"), None, 20000),
(SimParams46(7, 1, 600, _3e10), None, 20000),
(SimParams46(4, 2, 600, "2e10"), None, 20000),
]
@@ -322,8 +336,11 @@ def filter_meas(
key = lambda v: v[0].tuple
)
def get_meas(p: SimParams) -> Piecewise:
return measurements[p.machine_name][3]
def get_meas(params: SimParams) -> Piecewise:
pw = measurements[params.machine_name][3]
if params.is_discharge_high:
pw = pw.logically_inverted_xy()
return pw
def set_meas(real: str, expr: str):
pw = eval(expr)
@@ -3256,6 +3273,7 @@ Piecewise(
set_meas("42-0.00059999997rad-10coupling-5_1_winding-1e10-drive", """
Piecewise(
[
[ -17078, -2357 ], # -1.00
[ 16945, -16736 ], # 1.00
]
)
@@ -3702,6 +3720,15 @@ Piecewise(
)
""")
set_meas("46-0.00059999997rad-7coupling-3_1_winding-2e10-drive", """
Piecewise(
[
[ -16879, 16505 ], # -1.00, M1=10842
[ 16840, 15033 ], # 1.00, M1= 2034
]
)
""")
set_meas("46-0.00059999997rad-4coupling-5_1_winding-2e10-drive", """
Piecewise(
[

10
crates/applications/stacked_cores/src/main.rs
View File

@@ -1112,6 +1112,8 @@ fn drive_map_3stack_with_init_inv_then_buff(amp0: f32) -> [[ClockState; 3]; 5] {
// open S2 for receive
[C::hold_high(), C::float(), C::release_high()],
// write S1 -> S2
// TODO: we could try releasing S0 first.
// for 46-xx, this might reduce interference between S0 ctrl and S2?
[C::hold_high(), C::hold_high(), C::float()],
]
}
@@ -4420,7 +4422,7 @@ fn main() {
}
}
if true {
if false {
let p42xx = params_v2
.with_clock_phase_duration(ps(1000))
.with_clock_decay(ps(50))
@@ -4874,7 +4876,7 @@ fn main() {
}
}
if false {
if true {
let p46xx = params_v2
.with_clock_phase_duration(ps(1000))
.with_clock_decay(ps(50))
@@ -4899,7 +4901,11 @@ fn main() {
] {
for (coupling_loops, s0_loops, s_major, cur_flt) in [
(5, 1, um(400), 1e10), // verified geom;
(7, 1, um(600), 8e9),
(7, 1, um(600), 1e10),
(7, 1, um(600), 2e10),
(7, 1, um(600), 5e9),
(7, 1, um(600), 3e10),
(5, 1, um(400), 5e9),
(4, 2, um(600), 2e10),
(5, 1, um(400), 8e9),