colin/fdtd-coremem
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

spirv_backend: remove UVec3Std in favor of Vec3u

Browse Source
This commit is contained in:
colin
2022-07-18 13:39:15 -07:00
parent b4783df134
commit d7d8be62d1
4 changed files with 43 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
crates/spirv_backend/src/lib.rs
View File

@@ -17,18 +17,20 @@ pub mod sim;
pub mod support;
pub use sim::{SerializedSimMeta, SerializedStepE, SerializedStepH};
pub use support::{Optional, UnsizedArray, UVec3Std, Vec3Std};
pub use support::{Optional, UnsizedArray, Vec3Std};
use mat::{IsoConductorOr, Ferroxcube3R1MH, FullyGenericMaterial, Material};
use coremem_types::vecu::Vec3u;
type Iso3R1 = IsoConductorOr<Ferroxcube3R1MH>;
fn glam_vec_to_internal(v: UVec3) -> UVec3Std {
UVec3Std::new(v.x, v.y, v.z)
fn glam_vec_to_internal(v: UVec3) -> Vec3u {
Vec3u::new(v.x, v.y, v.z)
}
fn step_h<M: Material>(
id: UVec3Std,
id: Vec3u,
meta: &SerializedSimMeta,
stimulus_h: &UnsizedArray<Vec3Std>,
material: &UnsizedArray<M>,
@@ -44,7 +46,7 @@ fn step_h<M: Material>(
}
fn step_e<M: Material>(
id: UVec3Std,
id: Vec3u,
meta: &SerializedSimMeta,
stimulus_e: &UnsizedArray<Vec3Std>,
material: &UnsizedArray<M>,