coremem_types: enum: verify that setting the discriminant works as expected

This commit is contained in:
2022-07-21 21:16:43 -07:00
parent c889ec6d09
commit e96f0db11a

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@@ -27,10 +27,15 @@ impl<P: Peano> DiscriminantCodable<P> for Discr<P> {
} }
impl<P: Peano> Discr<P> { impl<P: Peano> Discr<P> {
pub fn new(u: u32) -> Self {
assert!(u < P::VALUE);
Self::new_unchecked(u)
}
fn new_unchecked(u: u32) -> Self { fn new_unchecked(u: u32) -> Self {
Self(u, Default::default()) Self(u, Default::default())
} }
} }
impl<P: Peano> Discr<P> { impl<P: Peano> Discr<P> {
fn dispatch<H: DiscrHandler<P, O>, O>(&self, h: H) -> O { fn dispatch<H: DiscrHandler<P, O>, O>(&self, h: H) -> O {
match self.0 { match self.0 {
@@ -153,17 +158,22 @@ mod test {
use super::*; use super::*;
#[test] #[test]
fn dispatch() { fn dispatch() {
struct Receiver { struct Receiver;
returns: f32, impl<P: Peano, T: TryInto<i32>> VariantHandler<P, T, i32> for Receiver {
} fn call(&self, v: T) -> i32 {
impl<P: Peano, T> VariantHandler<P, T, f32> for Receiver { unsafe {
fn call(&self, _: T) -> f32 { v.try_into().unwrap_unchecked() + P::VALUE as i32 + 5
self.returns }
} }
} }
let e: Enum<(Discr<P2>,), List<(u32, f32)>> = Enum::default(); let mut e: Enum<(Discr<P3>,), List<(u32, i32, u8)>> = Enum::default();
let r = Receiver { returns: 5f32 }; assert_eq!(e.dispatch(Receiver), 5);
assert_eq!(e.dispatch(r), 5f32);
e.encode_discr(Discr::new(1));
assert_eq!(e.dispatch(Receiver), 6);
e.encode_discr(Discr::new(2));
assert_eq!(e.dispatch(Receiver), 7);
} }
} }