colin 68d8cdde42 move some of the VolumeSample instantiation into step.rs, out of cpu.rs ...

we can go further: the IndexDim type itself can be moved into step.rs -- maybe?
if it were to wrap a generic flat-indexable thing -- either a slice, or
an array ref.

2022-07-26 01:15:53 -07:00

..

benches

coremem_types: IsomorphicConductor, AnisomorphicConductor are now used by both spirv and cpu impls

2022-07-19 02:08:22 -07:00

src

move some of the VolumeSample instantiation into step.rs, out of cpu.rs

2022-07-26 01:15:53 -07:00

Cargo.toml

coremem_types: add a 'fmt' feature, so Real/Vec/friends can be used in fmt-less spirv

2022-07-18 01:31:00 -07:00