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riscv: dts: jh7110: Add PLL clock controller node

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Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Xingyu Wu
2023-07-07 18:50:08 +08:00
committed by Leo Yu-Chi Liang
parent 2d7a578791
commit 005f9627d0
1 changed files with 7 additions and 1 deletions
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8
arch/riscv/dts/jh7110.dtsi
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@@ -498,8 +498,14 @@
};
sys_syscon: sys_syscon@13030000 {
compatible = "starfive,jh7110-sys-syscon","syscon";
compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
reg = <0x0 0x13030000 0x0 0x1000>;
pllclk: clock-controller {
compatible = "starfive,jh7110-pll";
clocks = <&osc>;
#clock-cells = <1>;
};
};
sysgpio: pinctrl@13040000 {