arm: socfpga: agilex5: Add SMMU initialization
Allow non-secure accesses only with SMMU peripherals. This would protect the content in DDR secure region from accidentally modified by SMMU peripherals. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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@@ -388,6 +388,40 @@
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bootph-all;
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};
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};
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socfpga_smmu_secure_config: socfpga-smmu-secure-config {
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compatible = "intel,socfpga-dtreg";
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#address-cells = <1>;
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#size-cells = <1>;
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bootph-all;
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/* System manager */
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i_sys_mgt_sysmgr_csr@10d12000 {
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reg = <0x10d12000 0x00000500>;
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intel,offset-settings =
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/* dma_tbu_stream_ctrl_reg_0_dma0 */
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<0x0000017c 0x00000000 0x0000003f>,
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/* dma_tbu_stream_ctrl_reg_0_dma1 */
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<0x00000180 0x00000000 0x0000003f>,
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/* sdm_tbu_stream_ctrl_reg_1_sdm */
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<0x00000184 0x00000000 0x0000003f>,
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/* io_tbu_stream_ctrl_reg_2_usb2 */
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<0x00000188 0x00000000 0x0000003f>,
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/* io_tbu_stream_ctrl_reg_2_sdmmc */
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<0x00000190 0x00000000 0x0000003f>,
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/* io_tbu_stream_ctrl_reg_2_nand */
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<0x00000194 0x00000000 0x0000003f>,
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/* io_tbu_stream_ctrl_reg_2_etr */
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<0x00000198 0x00000000 0x0000003f>,
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/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
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<0x0000019c 0x00000000 0x0000003f>,
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/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
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<0x000001a0 0x00000000 0x0000003f>,
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/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
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<0x000001a4 0x00000000 0x0000003f>;
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bootph-all;
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};
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};
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};
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};
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@@ -1,10 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#include <hang.h>
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#include <spl.h>
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#include <dm/uclass.h>
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DECLARE_GLOBAL_DATA_PTR;
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@@ -22,3 +25,16 @@ u32 spl_boot_mode(const u32 boot_device)
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return MMCSD_MODE_RAW;
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}
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#endif
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/* board specific function prior loading SSBL / U-Boot */
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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int ret;
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struct udevice *dev;
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev);
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if (ret) {
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printf("HPS SMMU secure settings init failed: %d\n", ret);
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hang();
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}
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}
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