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clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock

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Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
2024-08-03 10:43:25 +02:00
committed by Tom Rini
parent a776493f4b
commit 105c78844a
2 changed files with 51 additions and 30 deletions
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22
drivers/clk/mediatek/clk-mt7622.c
View File

@@ -422,6 +422,18 @@ static const struct mtk_gate infra_cgs[] = {
};
/* pericfg */
static const int peribus_ck_parents[] = {
CLK_TOP_SYSPLL1_D8,
CLK_TOP_SYSPLL1_D4,
};
#define PERI_MUX(_id, _parents, _reg, _shift, _width) \
MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN)
static const struct mtk_composite peri_muxes[] = {
PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1),
};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
@@ -602,6 +614,14 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = {
.gates = infra_cgs,
};
static const struct mtk_clk_tree mt7622_peri_clk_tree = {
.xtal_rate = 25 * MHZ,
.muxes_offs = CLK_PERIBUS_SEL,
.gates_offs = CLK_PERI_THERM_PD,
.muxes = peri_muxes,
.gates = peri_cgs,
};
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
@@ -658,7 +678,7 @@ static int mt7622_infracfg_probe(struct udevice *dev)
static int mt7622_pericfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree);
}
static int mt7622_pciesys_probe(struct udevice *dev)

59
include/dt-bindings/clock/mt7622-clk.h
View File

@@ -130,35 +130,36 @@
/* PERICFG */
#define CLK_PERI_THERM_PD 0
#define CLK_PERI_PWM1_PD 1
#define CLK_PERI_PWM2_PD 2
#define CLK_PERI_PWM3_PD 3
#define CLK_PERI_PWM4_PD 4
#define CLK_PERI_PWM5_PD 5
#define CLK_PERI_PWM6_PD 6
#define CLK_PERI_PWM7_PD 7
#define CLK_PERI_PWM_PD 8
#define CLK_PERI_AP_DMA_PD 9
#define CLK_PERI_MSDC30_0_PD 10
#define CLK_PERI_MSDC30_1_PD 11
#define CLK_PERI_UART0_PD 12
#define CLK_PERI_UART1_PD 13
#define CLK_PERI_UART2_PD 14
#define CLK_PERI_UART3_PD 15
#define CLK_PERI_UART4_PD 16
#define CLK_PERI_BTIF_PD 17
#define CLK_PERI_I2C0_PD 18
#define CLK_PERI_I2C1_PD 19
#define CLK_PERI_I2C2_PD 20
#define CLK_PERI_SPI1_PD 21
#define CLK_PERI_AUXADC_PD 22
#define CLK_PERI_SPI0_PD 23
#define CLK_PERI_SNFI_PD 24
#define CLK_PERI_NFI_PD 25
#define CLK_PERI_NFIECC_PD 26
#define CLK_PERI_FLASH_PD 27
#define CLK_PERI_IRTX_PD 28
#define CLK_PERIBUS_SEL 0
#define CLK_PERI_THERM_PD 1
#define CLK_PERI_PWM1_PD 2
#define CLK_PERI_PWM2_PD 3
#define CLK_PERI_PWM3_PD 4
#define CLK_PERI_PWM4_PD 5
#define CLK_PERI_PWM5_PD 6
#define CLK_PERI_PWM6_PD 7
#define CLK_PERI_PWM7_PD 8
#define CLK_PERI_PWM_PD 9
#define CLK_PERI_AP_DMA_PD 10
#define CLK_PERI_MSDC30_0_PD 11
#define CLK_PERI_MSDC30_1_PD 12
#define CLK_PERI_UART0_PD 13
#define CLK_PERI_UART1_PD 14
#define CLK_PERI_UART2_PD 15
#define CLK_PERI_UART3_PD 16
#define CLK_PERI_UART4_PD 17
#define CLK_PERI_BTIF_PD 18
#define CLK_PERI_I2C0_PD 19
#define CLK_PERI_I2C1_PD 20
#define CLK_PERI_I2C2_PD 21
#define CLK_PERI_SPI1_PD 22
#define CLK_PERI_AUXADC_PD 23
#define CLK_PERI_SPI0_PD 24
#define CLK_PERI_SNFI_PD 25
#define CLK_PERI_NFI_PD 26
#define CLK_PERI_NFIECC_PD 27
#define CLK_PERI_FLASH_PD 28
#define CLK_PERI_IRTX_PD 29
/* APMIXEDSYS */