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spi: cadence_qspi: Fix OSPI DDR mode alignment issue

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If the least significant bit of the address is set to one when
using the DDR protocol for data transfer then the results are
indeterminate for few flash devices. To fix this the least
significant bit of the address is set to zero.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250106095120.800753-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Padmarao Begari
2025-01-06 15:21:20 +05:30
committed by Michal Simek
parent a1319b5487
commit 1621851495
1 changed files with 12 additions and 0 deletions
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12
drivers/spi/cadence_ospi_versal.c
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@@ -24,6 +24,13 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
n_rx = op->data.nbytes;
if (op->addr.dtr && (op->addr.val % 2)) {
n_rx += 1;
writel(op->addr.val & ~0x1,
priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
}
rxbuf = op->data.buf.in;
rx_rem = n_rx % 4;
bytes_to_dma = n_rx - rx_rem;
@@ -104,6 +111,11 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
memcpy(rxbuf, &data, rx_rem);
}
if (op->addr.dtr && (op->addr.val % 2)) {
rxbuf -= bytes_to_dma;
memcpy(rxbuf, rxbuf + 1, n_rx - 1);
}
return 0;
}