xpl: Rename spl_phase() to xpl_phase()
Rename this function to indicate that it refers to any xPL phase. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
6
README
6
README
@@ -1512,7 +1512,7 @@ Low Level (hardware related) configuration options:
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Set when the currently running compilation is for an artifact
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that will end up in one of the 'xPL' builds, i.e. SPL, TPL or
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VPL. Code that needs phase-specific behaviour can check this,
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or (where possible) use spl_phase() instead.
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or (where possible) use xpl_phase() instead.
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Note that CONFIG_SPL_BUILD *is* always defined when either
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of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
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@@ -1522,13 +1522,13 @@ Low Level (hardware related) configuration options:
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Set when the currently running compilation is for an artifact
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that will end up in the TPL build (as opposed to SPL, VPL or
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U-Boot proper). Code that needs phase-specific behaviour can
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check this, or (where possible) use spl_phase() instead.
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check this, or (where possible) use xpl_phase() instead.
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- CONFIG_VPL_BUILD
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Set when the currently running compilation is for an artifact
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that will end up in the VPL build (as opposed to the SPL, TPL
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or U-Boot proper). Code that needs phase-specific behaviour can
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check this, or (where possible) use spl_phase() instead.
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check this, or (where possible) use xpl_phase() instead.
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- CONFIG_ARCH_MAP_SYSMEM
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Generally U-Boot (and in particular the md command) uses
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@@ -27,7 +27,7 @@ int sandbox_find_next_phase(char *fname, int maxlen, bool use_img)
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const char *cur_prefix, *next_prefix;
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int ret;
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cur_prefix = spl_phase_prefix(spl_phase());
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cur_prefix = spl_phase_prefix(xpl_phase());
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next_prefix = spl_phase_prefix(spl_next_phase());
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ret = os_find_u_boot(fname, maxlen, use_img, cur_prefix, next_prefix);
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if (ret)
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@@ -206,7 +206,7 @@ static int sandbox_cmdline_cb_test_fdt(struct sandbox_state *state,
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char *relname;
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int len;
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if (spl_phase() <= PHASE_SPL)
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if (xpl_phase() <= PHASE_SPL)
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relname = "../arch/sandbox/dts/test.dtb";
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else
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relname = "arch/sandbox/dts/test.dtb";
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@@ -184,9 +184,9 @@ int arch_cpu_init(void)
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{
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int ret = 0;
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if (spl_phase() == PHASE_TPL)
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if (xpl_phase() == PHASE_TPL)
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ret = arch_cpu_init_tpl();
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else if (spl_phase() == PHASE_SPL)
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else if (xpl_phase() == PHASE_SPL)
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ret = arch_cpu_init_spl();
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if (ret)
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printf("%s: Error %d\n", __func__, ret);
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@@ -255,7 +255,7 @@ static int apl_hostbridge_of_to_plat(struct udevice *dev)
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static int apl_hostbridge_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL)
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if (xpl_phase() == PHASE_TPL)
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return apl_hostbridge_early_init(dev);
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return 0;
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@@ -80,7 +80,7 @@ int lpc_open_pmio_window(uint base, uint size)
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lgir_reg_num = find_unused_pmio_window();
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if (lgir_reg_num < 0) {
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if (spl_phase() > PHASE_TPL) {
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if (xpl_phase() > PHASE_TPL) {
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log_err("LPC: Cannot open IO window: %lx size %lx\n",
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bridge_base, size - bridged_size);
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log_err("No more IO windows\n");
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@@ -12,7 +12,7 @@
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static int apl_set_spi_protect(struct udevice *dev, bool protect)
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{
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if (spl_phase() == PHASE_SPL)
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if (xpl_phase() == PHASE_SPL)
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return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
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return 0;
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@@ -115,7 +115,7 @@ int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
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ARRAY_SIZE(base));
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if (ret)
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return log_msg_ret("Missing/short early-regs", ret);
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if (spl_phase() == PHASE_TPL) {
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if (xpl_phase() == PHASE_TPL) {
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upriv->pmc_bar0 = (void *)base[0];
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upriv->pmc_bar2 = (void *)base[2];
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@@ -186,7 +186,7 @@ static int enable_pmcbar(struct udevice *dev)
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static int apl_pmc_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL) {
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if (xpl_phase() == PHASE_TPL) {
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return enable_pmcbar(dev);
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} else {
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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@@ -77,7 +77,7 @@ static int punit_init(struct udevice *dev)
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static int apl_punit_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_SPL)
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if (xpl_phase() == PHASE_SPL)
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return punit_init(dev);
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return 0;
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@@ -116,7 +116,7 @@ static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
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return ret;
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spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
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spl_image->entry_point = spl_phase() == PHASE_TPL ?
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spl_image->entry_point = xpl_phase() == PHASE_TPL ?
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CONFIG_SPL_TEXT_BASE : CONFIG_TEXT_BASE;
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spl_image->load_addr = spl_image->entry_point;
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spl_image->os = IH_OS_U_BOOT;
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@@ -68,7 +68,7 @@ int arch_cpu_init(void)
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post_code(POST_CPU_INIT);
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/* Do a mini-init if TPL has already done the full init */
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if (IS_ENABLED(CONFIG_TPL) && spl_phase() != PHASE_TPL)
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if (IS_ENABLED(CONFIG_TPL) && xpl_phase() != PHASE_TPL)
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return x86_cpu_reinit_f();
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else
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return x86_cpu_init_f();
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@@ -271,7 +271,7 @@ static void identify_cpu(struct cpu_device_id *cpu)
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* Do a quick and dirty check to save space - Intel and AMD only and
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* just the vendor. This is enough for most TPL code.
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*/
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if (spl_phase() == PHASE_TPL) {
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if (xpl_phase() == PHASE_TPL) {
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struct cpuid_result result;
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result = cpuid(0x00000000);
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@@ -259,7 +259,7 @@ int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
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return ret;
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delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
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if (spl_phase() == PHASE_SPL) {
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if (xpl_phase() == PHASE_SPL) {
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if (delay)
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printf("SDRAM training (%d seconds)...", delay);
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else
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@@ -96,7 +96,7 @@ int p2sb_of_to_plat(struct udevice *dev)
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return log_msg_ret("Missing/short early-regs", ret);
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plat->mmio_base = base[0];
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/* TPL sets up the initial BAR */
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if (spl_phase() == PHASE_TPL) {
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if (xpl_phase() == PHASE_TPL) {
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plat->bdf = pci_get_devfn(dev);
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if (plat->bdf < 0)
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return log_msg_ret("Cannot get p2sb PCI address",
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@@ -114,9 +114,9 @@ int p2sb_of_to_plat(struct udevice *dev)
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static int p2sb_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL)
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if (xpl_phase() == PHASE_TPL)
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return p2sb_early_init(dev);
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else if (spl_phase() == PHASE_SPL)
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else if (xpl_phase() == PHASE_SPL)
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return p2sb_spl_init(dev);
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return 0;
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@@ -28,7 +28,7 @@ int dram_init(void)
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return 0;
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}
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if (spl_phase() == PHASE_SPL) {
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if (xpl_phase() == PHASE_SPL) {
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bool s3wake = false;
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s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
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@@ -25,7 +25,7 @@ int fsp_setup_pinctrl(void)
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int ret;
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/* Make sure pads are set up early in U-Boot */
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if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F)
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if (!ll_boot_init() || xpl_phase() != PHASE_BOARD_F)
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return 0;
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/* Probe all pinctrl devices to set up the pads */
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@@ -134,7 +134,7 @@ int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
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return log_msg_ret("Could not get flash mmap", ret);
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}
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if (spl_phase() >= PHASE_BOARD_F) {
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if (xpl_phase() >= PHASE_BOARD_F) {
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if (type != FSP_S)
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return -EPROTONOSUPPORT;
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ret = binman_entry_find("intel-fsp-s", entry);
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@@ -27,7 +27,7 @@ static int fdt_simplefb_configure_node(void *blob, int off)
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struct udevice *dev;
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int ret;
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if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) {
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if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) {
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struct video_handoff *ho;
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ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
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@@ -157,7 +157,7 @@ static int simple_load_from_image(struct spl_image_info *spl_image,
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struct vbe_handoff *handoff;
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int ret;
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if (spl_phase() != PHASE_VPL && spl_phase() != PHASE_SPL)
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if (xpl_phase() != PHASE_VPL && xpl_phase() != PHASE_SPL)
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return -ENOENT;
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ret = bloblist_ensure_size(BLOBLISTT_VBE, sizeof(struct vbe_handoff),
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@@ -197,7 +197,7 @@ static int simple_load_from_image(struct spl_image_info *spl_image,
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bootflow_free(&bflow);
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/* Record that VBE was used in this phase */
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handoff->phases |= 1 << spl_phase();
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handoff->phases |= 1 << xpl_phase();
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return 0;
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}
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@@ -397,7 +397,7 @@ __weak int arch_reserve_mmu(void)
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static int reserve_video_from_videoblob(void)
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{
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if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL) {
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if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) {
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struct video_handoff *ho;
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int ret = 0;
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@@ -489,7 +489,7 @@ int bootstage_unstash(const void *base, int size)
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for (rec = data->record + data->next_id, i = 0; i < hdr->count;
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i++, rec++) {
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rec->name = ptr;
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if (spl_phase() == PHASE_SPL)
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if (xpl_phase() == PHASE_SPL)
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rec->name = strdup(ptr);
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/* Assume no data corruption here */
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@@ -441,7 +441,7 @@ static inline int write_spl_handoff(void) { return 0; }
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*/
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static enum bootstage_id get_bootstage_id(bool start)
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{
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enum xpl_phase_t phase = spl_phase();
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enum xpl_phase_t phase = xpl_phase();
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if (IS_ENABLED(CONFIG_TPL_BUILD) && phase == PHASE_TPL)
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return start ? BOOTSTAGE_ID_START_TPL : BOOTSTAGE_ID_END_TPL;
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@@ -476,7 +476,7 @@ static int spl_common_init(bool setup_malloc)
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log_debug("Failed to unstash bootstage: ret=%d\n", ret);
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}
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bootstage_mark_name(get_bootstage_id(true),
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spl_phase_name(spl_phase()));
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spl_phase_name(xpl_phase()));
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#if CONFIG_IS_ENABLED(LOG)
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ret = log_init();
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if (ret) {
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@@ -493,7 +493,7 @@ static int spl_common_init(bool setup_malloc)
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}
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if (CONFIG_IS_ENABLED(DM)) {
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bootstage_start(BOOTSTAGE_ID_ACCUM_DM_SPL,
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spl_phase() == PHASE_TPL ? "dm tpl" : "dm_spl");
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xpl_phase() == PHASE_TPL ? "dm tpl" : "dm_spl");
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/* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
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ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
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bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_SPL);
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@@ -34,6 +34,8 @@ For example::
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foo();
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#endif
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if (xpl_phase() == PHASE_TPL)
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bar();
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The building of SPL images can be enabled by CONFIG_SPL option in Kconfig.
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@@ -117,7 +119,7 @@ Further usages of U-Boot SPL comprise:
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Checking the boot phase
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-----------------------
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Use `spl_phase()` to find the current U-Boot phase, e.g. `PHASE_SPL`. You can
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Use `xpl_phase()` to find the current U-Boot phase, e.g. `PHASE_SPL`. You can
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also find the previous and next phase and get the phase name.
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@@ -37,7 +37,7 @@ static int designware_i2c_pci_of_to_plat(struct udevice *dev)
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{
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struct dw_i2c *priv = dev_get_priv(dev);
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if (spl_phase() < PHASE_SPL) {
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if (xpl_phase() < PHASE_SPL) {
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u32 base;
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int ret;
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@@ -53,7 +53,7 @@ static int designware_i2c_pci_of_to_plat(struct udevice *dev)
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PCI_COMMAND_MASTER);
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}
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if (spl_phase() < PHASE_BOARD_F) {
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if (xpl_phase() < PHASE_BOARD_F) {
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/* Handle early, fixed mapping into a different address space */
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priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
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} else {
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@@ -198,7 +198,7 @@ static int p2sb_child_post_bind(struct udevice *dev)
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static int p2sb_post_bind(struct udevice *dev)
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{
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if (spl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA))
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if (xpl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA))
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return dm_scan_fdt_dev(dev);
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return 0;
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@@ -722,7 +722,7 @@ static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
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u32 vendev;
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int index;
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if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP))
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if (xpl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP))
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return true;
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for (index = 0;
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@@ -798,7 +798,7 @@ static int pci_find_and_bind_driver(struct udevice *parent,
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if (!(gd->flags & GD_FLG_RELOC) &&
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!(drv->flags & DM_FLAG_PRE_RELOC) &&
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(!CONFIG_IS_ENABLED(PCI_PNP) ||
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spl_phase() != PHASE_SPL))
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xpl_phase() != PHASE_SPL))
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return log_msg_ret("pre", -EPERM);
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/*
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@@ -379,7 +379,7 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void))
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}
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/* In U-Boot proper, collect the information added by SPL (see below) */
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if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL &&
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if (IS_ENABLED(CONFIG_SPL_VIDEO) && xpl_phase() > PHASE_SPL &&
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CONFIG_IS_ENABLED(BLOBLIST)) {
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struct video_handoff *ho;
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@@ -425,7 +425,7 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void))
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mode_info.vesa.bits_per_pixel);
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/* In SPL, store the information for use by U-Boot proper */
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if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
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if (xpl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
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struct video_handoff *ho;
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ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
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@@ -273,7 +273,7 @@ static int pinctrl_configure_itss(struct udevice *dev,
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irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset));
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irq &= PAD_CFG1_IRQ_MASK;
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if (!irq) {
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if (spl_phase() > PHASE_TPL)
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if (xpl_phase() > PHASE_TPL)
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log_err("GPIO %u doesn't support APIC routing\n",
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cfg->pad);
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@@ -315,7 +315,7 @@ static int pinctrl_pad_reset_config_override(const struct pad_community *comm,
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return config_value;
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}
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}
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if (spl_phase() > PHASE_TPL)
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if (xpl_phase() > PHASE_TPL)
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log_err("Logical-to-Chipset mapping not found\n");
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return -ENOENT;
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@@ -622,7 +622,7 @@ int intel_pinctrl_of_to_plat(struct udevice *dev,
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struct intel_pinctrl_priv *priv = dev_get_priv(dev);
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if (!comm) {
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if (spl_phase() > PHASE_TPL)
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if (xpl_phase() > PHASE_TPL)
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log_err("Cannot find community for pid %d\n",
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pplat->pid);
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return -EDOM;
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@@ -60,7 +60,7 @@ int pmc_gpe_init(struct udevice *dev)
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* are different and if they aren't, use the reset values.
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*/
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if (dw[0] == dw[1] || dw[1] == dw[2]) {
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if (spl_phase() > PHASE_TPL)
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if (xpl_phase() > PHASE_TPL)
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log_info("PMC: Using default GPE route");
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gpio_cfg = readl(upriv->gpe_cfg);
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for (i = 0; i < upriv->gpe0_count; i++)
|
||||
|
@@ -193,7 +193,7 @@ struct io_setting {
|
||||
*/
|
||||
static bool phase_sdram_init(void)
|
||||
{
|
||||
return spl_phase() == PHASE_TPL ||
|
||||
return xpl_phase() == PHASE_TPL ||
|
||||
(!IS_ENABLED(CONFIG_TPL) &&
|
||||
!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL) &&
|
||||
!spl_in_proper());
|
||||
|
@@ -779,7 +779,7 @@ static int ich_init_controller(struct udevice *dev,
|
||||
struct ich_spi_plat *plat,
|
||||
struct ich_spi_priv *ctlr)
|
||||
{
|
||||
if (spl_phase() == PHASE_TPL) {
|
||||
if (xpl_phase() == PHASE_TPL) {
|
||||
struct ich_spi_plat *plat = dev_get_plat(dev);
|
||||
int ret;
|
||||
|
||||
@@ -867,7 +867,7 @@ static int ich_spi_probe(struct udevice *dev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (spl_phase() == PHASE_TPL) {
|
||||
if (xpl_phase() == PHASE_TPL) {
|
||||
/* Cache the BIOS to speed things up */
|
||||
ret = ich_cache_bios_region(dev);
|
||||
if (ret)
|
||||
|
@@ -102,7 +102,7 @@ void sysreset_walk_halt(enum sysreset_t type)
|
||||
mdelay(100);
|
||||
|
||||
/* Still no reset? Give up */
|
||||
if (spl_phase() <= PHASE_SPL)
|
||||
if (xpl_phase() <= PHASE_SPL)
|
||||
log_err("no sysreset\n");
|
||||
else
|
||||
log_err("System reset not supported on this platform\n");
|
||||
|
@@ -802,7 +802,7 @@ static int truetype_entry_save(struct udevice *dev, struct abuf *buf)
|
||||
struct console_tt_store store;
|
||||
const uint size = sizeof(store);
|
||||
|
||||
if (spl_phase() <= PHASE_SPL)
|
||||
if (xpl_phase() <= PHASE_SPL)
|
||||
return -ENOSYS;
|
||||
|
||||
/*
|
||||
@@ -826,7 +826,7 @@ static int truetype_entry_restore(struct udevice *dev, struct abuf *buf)
|
||||
struct console_tt_priv *priv = dev_get_priv(dev);
|
||||
struct console_tt_store store;
|
||||
|
||||
if (spl_phase() <= PHASE_SPL)
|
||||
if (xpl_phase() <= PHASE_SPL)
|
||||
return -ENOSYS;
|
||||
|
||||
memcpy(&store, abuf_data(buf), sizeof(store));
|
||||
@@ -853,7 +853,7 @@ static int truetype_set_cursor_visible(struct udevice *dev, bool visible,
|
||||
uint out, val;
|
||||
int ret;
|
||||
|
||||
if (spl_phase() <= PHASE_SPL)
|
||||
if (xpl_phase() <= PHASE_SPL)
|
||||
return -ENOSYS;
|
||||
|
||||
if (!visible)
|
||||
|
@@ -128,7 +128,7 @@ int video_reserve(ulong *addrp)
|
||||
struct udevice *dev;
|
||||
ulong size;
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() == PHASE_BOARD_F)
|
||||
if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() == PHASE_BOARD_F)
|
||||
return 0;
|
||||
|
||||
gd->video_top = *addrp;
|
||||
@@ -421,7 +421,7 @@ bool video_is_active(void)
|
||||
struct udevice *dev;
|
||||
|
||||
/* Assume video to be active if SPL passed video hand-off to U-boot */
|
||||
if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && spl_phase() > PHASE_SPL)
|
||||
if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL)
|
||||
return true;
|
||||
|
||||
for (uclass_find_first_device(UCLASS_VIDEO, &dev);
|
||||
@@ -573,7 +573,7 @@ static int video_post_probe(struct udevice *dev)
|
||||
* NOTE:
|
||||
* This assumes that reserved video memory only uses a single framebuffer
|
||||
*/
|
||||
if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
|
||||
if (xpl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
|
||||
struct video_handoff *ho;
|
||||
|
||||
ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
|
||||
|
@@ -74,7 +74,7 @@ enum xpl_phase_t {
|
||||
};
|
||||
|
||||
/**
|
||||
* spl_phase() - Find out the phase of U-Boot
|
||||
* xpl_phase() - Find out the phase of U-Boot
|
||||
*
|
||||
* This can be used to avoid #ifdef logic and use if() instead.
|
||||
*
|
||||
@@ -86,7 +86,7 @@ enum xpl_phase_t {
|
||||
*
|
||||
* but with this you can use:
|
||||
*
|
||||
* if (spl_phase() == PHASE_TPL) {
|
||||
* if (xpl_phase() == PHASE_TPL) {
|
||||
* ...
|
||||
* }
|
||||
*
|
||||
@@ -98,7 +98,7 @@ enum xpl_phase_t {
|
||||
*
|
||||
* but with this you can use:
|
||||
*
|
||||
* if (spl_phase() == PHASE_SPL) {
|
||||
* if (xpl_phase() == PHASE_SPL) {
|
||||
* ...
|
||||
* }
|
||||
*
|
||||
@@ -110,13 +110,13 @@ enum xpl_phase_t {
|
||||
*
|
||||
* but with this you can use:
|
||||
*
|
||||
* if (spl_phase() == PHASE_BOARD_F) {
|
||||
* if (xpl_phase() == PHASE_BOARD_F) {
|
||||
* ...
|
||||
* }
|
||||
*
|
||||
* Return: U-Boot phase
|
||||
*/
|
||||
static inline enum xpl_phase_t spl_phase(void)
|
||||
static inline enum xpl_phase_t xpl_phase(void)
|
||||
{
|
||||
#ifdef CONFIG_TPL_BUILD
|
||||
return PHASE_TPL;
|
||||
|
@@ -608,7 +608,7 @@ int fdtdec_get_chosen_node(const void *blob, const char *name)
|
||||
static int fdtdec_prepare_fdt(const void *blob)
|
||||
{
|
||||
if (!blob || ((uintptr_t)blob & 3) || fdt_check_header(blob)) {
|
||||
if (spl_phase() <= PHASE_SPL) {
|
||||
if (xpl_phase() <= PHASE_SPL) {
|
||||
puts("Missing DTB\n");
|
||||
} else {
|
||||
printf("No valid device tree binary found at %p\n",
|
||||
|
@@ -749,9 +749,9 @@ int lmb_init(void)
|
||||
lmb_add_memory();
|
||||
|
||||
/* Reserve the U-Boot image region once U-Boot has relocated */
|
||||
if (spl_phase() == PHASE_SPL)
|
||||
if (xpl_phase() == PHASE_SPL)
|
||||
lmb_reserve_common_spl();
|
||||
else if (spl_phase() == PHASE_BOARD_R)
|
||||
else if (xpl_phase() == PHASE_BOARD_R)
|
||||
lmb_reserve_common((void *)gd->fdt_blob);
|
||||
|
||||
return 0;
|
||||
|
@@ -100,7 +100,7 @@ uint64_t notrace get_ticks(void)
|
||||
|
||||
ret = timer_get_count(gd->timer, &count);
|
||||
if (ret) {
|
||||
if (spl_phase() > PHASE_TPL)
|
||||
if (xpl_phase() > PHASE_TPL)
|
||||
panic("Could not read count from timer (err %d)\n",
|
||||
ret);
|
||||
else
|
||||
|
Reference in New Issue
Block a user