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usb: dwc3: fix dcache flush range calculation

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The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with CACHELINE_SIZE.

This causes operation failures Qualcomm platforms.

Take in account the alignment and size of the buffer and also
flush the previous and last cacheline.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20241011-u-boot-dwc3-gadget-dcache-fixup-v4-2-5f3498d8035b@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This commit is contained in:
Neil Armstrong
2024-10-11 16:38:25 +02:00
committed by Mattijs Korpershoek
parent 1f12fc7e33
commit 502a50ab1f
1 changed files with 4 additions and 1 deletions
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5
drivers/usb/dwc3/io.h
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@@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
static inline void dwc3_flush_cache(uintptr_t addr, int length)
{
flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1);
uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE);
flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr);
}
#endif /* __DRIVERS_USB_DWC3_IO_H */