board: bsh: imx6ulz_smm_m2: Add support for 512 MiB DRAM
Calibration values were calculated using the NXP tool I.MX6ULL_DDR3_Script_Aid_V0.01.xlsx Signed-off-by: Michael Bode <michael.bode@bshg.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This commit is contained in:
Michael Bode
committed by
Fabio Estevam
Fabio Estevam
parent
8c2987396a
commit
6c885d9ac6
@@ -2,5 +2,4 @@
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# (C) Copyright 2021 Amarula Solutions B.V.
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obj-y := imx6ulz_smm_m2.o
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obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_256m.o ddr3l_timing_128m.o
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obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o
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168
board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c
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168
board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c
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@@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include "spl_mtypes.h"
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static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = {
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/*
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* =============================================================================
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* IOMUX
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* =============================================================================
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*/
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/* DDR IO Type: */
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{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* Clock: */
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{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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/* Address: */
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{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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/* Control: */
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{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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{0x020e0270, 0x00000000}, /*
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using
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* Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
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*/
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{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* Data Strobes: */
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{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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/* Data: */
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{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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/*
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* =============================================================================
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* DDR Controller Registers
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* =============================================================================
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* Manufacturer:ISSI
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* Device Part Number:IS43TR16640BL-125JBLI
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* Clock Freq.: 400MHz
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* Density per CS in Gb: 2
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* Chip Selects used:1
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* Number of Banks:8
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* Row address: 14
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* Column address: 10
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* Data bus width16
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* =============================================================================
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*/
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request bit during
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* MMDC set up
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*/
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/*
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* =============================================================================
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* Calibration setup.
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* =============================================================================
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*/
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{0x021b0800, 0xA1390003}, /*
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* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
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* HW ZQ calibration
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*/
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/*
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* For target board may need to run write leveling calibration to fine tune these settings
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*/
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{0x021b080c, 0x00000000},
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/* Read DQS Gating calibration */
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{0x021b083c, 0x01440140}, /* MPDGCTRL0 PHY0 */
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/* Read calibration */
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{0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */
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/* Write calibration */
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{0x021b0850, 0x4040322A}, /* MPWRDLCTL PHY0 */
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/*
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* Read data bit delay: 3 is the reccommended default value, although out of reset value
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* is 0
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*/
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{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
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{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
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/* Write data bit delay: */
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{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
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{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
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/* DQS&CLK Duty Cycle */
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{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
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/* Complete calibration by forced measurement: */
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{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
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/*
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* =============================================================================
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* Calibration setup end
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* =============================================================================
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*/
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/* MMDC init: */
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{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
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{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
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{0x021b000c, 0x3F435333}, /* MMDC0_MDCFG0 */
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{0x021b0010, 0xB68E0B63}, /* MMDC0_MDCFG1 */
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{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
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/*
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* MDMISC: RALAT kept to the high level of 5.
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* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
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* Lower RALAT benefits:
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* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
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* b. Small performence improvment
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*/
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{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR set the Configuration request bit during
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* MMDC set up
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*/
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{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
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{0x021b0030, 0x00431023}, /* MMDC0_MDOR */
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{0x021b0040, 0x0000004F}, /* Chan0 CS0_END */
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{0x021b0000, 0x84180000}, /* MMDC0_MDCTL */
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{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
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/* Mode register writes */
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{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
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{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
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{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
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{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
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{0x021b001c, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
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{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
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{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
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{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
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{0x021b0404, 0x00011006}, /*
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* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter
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* automatically to self-refresh while the number of idle
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* cycle reached
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*/
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{0x021b001c, 0x00000000}, /*
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* MMDC0_MDSCR, clear this register (especially the configuration
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* bit as initialization is complete)
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*/
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};
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struct dram_timing_info bsh_dram_timing_512mb = {
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.ddrc_cfg = ddr_ddrc_cfg_512mb,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb),
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};
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@@ -54,16 +54,19 @@ static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
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static void spl_dram_init(void)
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{
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/* Configure memory to maximum supported size for detection */
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ddr_cfg_write(&bsh_dram_timing_256mb);
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ddr_cfg_write(&bsh_dram_timing_512mb);
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/* Detect memory physically present */
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_256M);
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
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/* Reconfigure memory for actual detected size */
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switch (gd->ram_size) {
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case SZ_256M:
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case SZ_512M:
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/* Already configured, nothing to do */
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break;
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case SZ_256M:
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ddr_cfg_write(&bsh_dram_timing_256mb);
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break;
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case SZ_128M:
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default:
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ddr_cfg_write(&bsh_dram_timing_128mb);
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@@ -22,5 +22,6 @@ struct dram_timing_info {
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extern struct dram_timing_info bsh_dram_timing_128mb;
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extern struct dram_timing_info bsh_dram_timing_256mb;
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extern struct dram_timing_info bsh_dram_timing_512mb;
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#endif /* SPL_MTYPES_H */
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