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Merge patch series "Arm: npcm: modify npcm8xx boot setting"

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Jim Liu <jim.t90615@gmail.com> says:

Modify npcm8xx new boot design.
Correct memory setting and set gpio default value.
This commit is contained in:
Tom Rini
2024-09-16 16:43:53 -06:00
parent fca70d6181 3aa2eac4f0
commit 773f138632
4 changed files with 27 additions and 5 deletions
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8
board/nuvoton/arbel_evb/arbel_evb.c
View File

@@ -59,17 +59,21 @@ int dram_init(void)
int dram_init_banksize(void) int dram_init_banksize(void)
{ {
phys_size_t ram_size = gd->ram_size;
gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].start = 0;
switch (gd->ram_size) { #if defined(CONFIG_SYS_MEM_TOP_HIDE)
ram_size += CONFIG_SYS_MEM_TOP_HIDE;
#endif
switch (ram_size) {
case DRAM_512MB_ECC_SIZE: case DRAM_512MB_ECC_SIZE:
case DRAM_512MB_SIZE: case DRAM_512MB_SIZE:
case DRAM_1GB_ECC_SIZE: case DRAM_1GB_ECC_SIZE:
case DRAM_1GB_SIZE: case DRAM_1GB_SIZE:
case DRAM_2GB_ECC_SIZE: case DRAM_2GB_ECC_SIZE:
case DRAM_2GB_SIZE: case DRAM_2GB_SIZE:
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = ram_size;
gd->bd->bi_dram[1].start = 0; gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0; gd->bd->bi_dram[1].size = 0;
break; break;

4
configs/arbel_evb_defconfig
View File

@@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x06208000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x06208000
CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_OFFSET=0x7C0000
CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb" CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb"
@@ -17,7 +17,7 @@ CONFIG_ARCH_NPCM8XX=y
CONFIG_SYS_SKIP_UART_INIT=y CONFIG_SYS_SKIP_UART_INIT=y
CONFIG_TARGET_ARBEL_EVB=y CONFIG_TARGET_ARBEL_EVB=y
CONFIG_SYS_LOAD_ADDR=0x06208000 CONFIG_SYS_LOAD_ADDR=0x06208000
CONFIG_ENV_ADDR=0x803C0000 CONFIG_ENV_ADDR=0x807C0000
CONFIG_FIT=y CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y CONFIG_FIT_VERBOSE=y
CONFIG_SYS_BOOTM_LEN=0x1400000 CONFIG_SYS_BOOTM_LEN=0x1400000

18
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
View File

@@ -48,6 +48,7 @@
#define GPIO_OES 0x70 /* Output Enable Set */ #define GPIO_OES 0x70 /* Output Enable Set */
#define GPIO_OEC 0x74 /* Output Enable Clear */ #define GPIO_OEC 0x74 /* Output Enable Clear */
#define NPCM8XX_NUM_GPIO_BANK 8
#define NPCM8XX_GPIO_PER_BANK 32 #define NPCM8XX_GPIO_PER_BANK 32
#define GPIOX_OFFSET 16 #define GPIOX_OFFSET 16
@@ -967,6 +968,18 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector,
} }
#endif #endif
static void npcm8xx_pinctrl_clear_events(struct npcm8xx_pinctrl_priv *priv)
{
void __iomem *base;
int i;
for (i = 0; i < NPCM8XX_NUM_GPIO_BANK; i++) {
base = priv->gpio_base + (0x1000 * i);
clrbits_le32(base + GPIO_EVEN, 0xFFFFFFFF);
setbits_le32(base + GPIO_EVST, 0xFFFFFFFF);
}
}
static struct pinctrl_ops npcm8xx_pinctrl_ops = { static struct pinctrl_ops npcm8xx_pinctrl_ops = {
.set_state = pinctrl_generic_set_state, .set_state = pinctrl_generic_set_state,
.get_pins_count = npcm8xx_get_pins_count, .get_pins_count = npcm8xx_get_pins_count,
@@ -1001,6 +1014,11 @@ static int npcm8xx_pinctrl_probe(struct udevice *dev)
if (IS_ERR(priv->rst_regmap)) if (IS_ERR(priv->rst_regmap))
return -EINVAL; return -EINVAL;
/*
* Clear all previous gpio events, otherwise it may produce
* unexpected interrupts during kernel booting.
*/
npcm8xx_pinctrl_clear_events(priv);
return 0; return 0;
} }

2
include/configs/arbel.h
View File

@@ -16,7 +16,7 @@
{ 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 } { 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
/* Default environemnt variables */ /* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \ #define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80800000\0" \
"stdin=serial\0" \ "stdin=serial\0" \
"stdout=serial\0" \ "stdout=serial\0" \
"stderr=serial\0" \ "stderr=serial\0" \