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Merge tag 'u-boot-dfu-20250211' of https://source.denx.de/u-boot/custodians/u-boot-dfu

Browse Source 
u-boot-dfu-20250211:

CI:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/24556

Android:
- Handle boot images with missing DTB

Usb gadget:
- Fix nullptr in g_dnl when serial# is unset
- Add missing schedule() in f_mass_storage gadget
- Add support for STih407 in dwc3-generic
- Fix usb clocks on STih407
- Migrate STih407 to DM_USB_GADGET
This commit is contained in:
Tom Rini
2025-02-11 08:56:54 -06:00
parent 636fcc96c3 4096d28ec8
commit 7f89b40f1c
15 changed files with 173 additions and 357 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@@ -671,8 +671,7 @@ F: drivers/reset/sti-reset.c
F: drivers/serial/serial_sti_asc.c
F: drivers/sysreset/sysreset_sti.c
F: drivers/timer/arm_global_timer.c
F: drivers/usb/host/dwc3-sti-glue.c
F: include/dwc3-sti-glue.h
F: drivers/usb/host/dwc3-sti.c
F: include/dt-bindings/clock/stih407-clks.h
F: include/dt-bindings/clock/stih410-clks.h
F: include/dt-bindings/reset/stih407-resets.h

10
arch/arm/dts/stih410-b2260-u-boot.dtsi
View File

@@ -14,20 +14,30 @@
};
};
clk_usb: clk-usb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
ohci0: usb@9a03c00 {
compatible = "generic-ohci";
clocks = <&clk_usb>;
};
ehci0: usb@9a03e00 {
compatible = "generic-ehci";
clocks = <&clk_usb>;
};
ohci1: usb@9a83c00 {
compatible = "generic-ohci";
clocks = <&clk_usb>;
};
ehci1: usb@9a83e00 {
compatible = "generic-ehci";
clocks = <&clk_usb>;
};
};
};

30
board/st/stih410-b2260/board.c
View File

@@ -7,11 +7,6 @@
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <linux/usb/otg.h>
#include <dwc3-sti-glue.h>
#include <dwc3-uboot.h>
#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,31 +38,6 @@ int board_init(void)
}
#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
};
int board_usb_init(int index, enum usb_init_type init)
{
int node;
const void *blob = gd->fdt_blob;
/* find the snps,dwc3 node */
node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg");
return dwc3_uboot_init(&dwc3_device_data);
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
dwc3_uboot_exit(index);
return 0;
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;

5
boot/image-android.c
View File

@@ -696,7 +696,10 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img,
ulong dtb_addr; /* address of DTB blob with specified index */
u32 i; /* index iterator */
android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr);
if (!android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img,
&dtb_img_addr))
return false;
/* Check if DTB area of boot image is in DTBO format */
if (android_dt_check_header(dtb_img_addr)) {
return android_dt_get_fdt_by_index(dtb_img_addr, index, addr,

5
configs/stih410-b2260_defconfig
View File

@@ -25,6 +25,7 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@@ -48,11 +49,13 @@ CONFIG_MMC_SDHCI_STI=y
CONFIG_PHY=y
CONFIG_STI_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR=y
CONFIG_STI_RESET=y
CONFIG_STI_ASC_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
@@ -60,6 +63,8 @@ CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_STI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y

8
drivers/usb/dwc3/Kconfig
View File

@@ -87,6 +87,14 @@ config USB_DWC3_LAYERSCAPE
Host and Peripheral operation modes are supported. OTG is not
supported.
config USB_DWC3_STI
bool "STi USB wrapper"
depends on DM_USB && USB_DWC3_GENERIC && SYSCON
help
Enables support for the on-chip xHCI controller on STMicroelectronics
STiH407 family SoCs. This is a driver for the dwc3 to provide the
glue logic to configure the controller.
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP

1
drivers/usb/dwc3/Makefile
View File

@@ -15,3 +15,4 @@ obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
obj-$(CONFIG_USB_DWC3_STI) += dwc3-generic-sti.o

134
drivers/usb/dwc3/dwc3-generic-sti.c Normal file
View File

@@ -0,0 +1,134 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* STi specific glue layer for DWC3
*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_NOP
#include <reset.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <dm/device.h>
#include <dm/device_compat.h>
#include <dm/read.h>
#include <linux/usb/otg.h>
#include "dwc3-generic.h"
/* glue registers */
#define CLKRST_CTRL 0x00
#define AUX_CLK_EN BIT(0)
#define SW_PIPEW_RESET_N BIT(4)
#define EXT_CFG_RESET_N BIT(8)
#define XHCI_REVISION BIT(12)
#define USB2_VBUS_MNGMNT_SEL1 0x2C
#define USB2_VBUS_UTMIOTG 0x1
#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0)
#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4)
#define SEL_OVERRIDE_BVALID(n) ((n) << 8)
/* Static DRD configuration */
#define USB3_CONTROL_MASK 0xf77
#define USB3_DEVICE_NOT_HOST BIT(0)
#define USB3_FORCE_VBUSVALID BIT(1)
#define USB3_DELAY_VBUSVALID BIT(2)
#define USB3_SEL_FORCE_OPMODE BIT(4)
#define USB3_FORCE_OPMODE(n) ((n) << 5)
#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8)
#define USB3_FORCE_DPPULLDOWN2 BIT(9)
#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10)
#define USB3_FORCE_DMPULLDOWN2 BIT(11)
static void dwc3_stih407_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
struct dwc3_glue_data *glue = dev_get_plat(dev);
struct regmap *regmap;
ulong syscfg_base;
ulong syscfg_offset;
ulong glue_base;
int ret;
/* deassert both powerdown and softreset */
ret = reset_deassert_bulk(&glue->resets);
if (ret) {
dev_err(dev, "reset_deassert_bulk error: %d\n", ret);
return;
}
regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg");
if (IS_ERR(regmap)) {
dev_err(dev, "unable to get st,syscfg, dev %s\n", dev->name);
return;
}
syscfg_base = regmap->ranges[0].start;
glue_base = dev_read_addr_index(dev, 0);
syscfg_offset = dev_read_addr_index(dev, 1);
clrbits_le32(syscfg_base + syscfg_offset, USB3_CONTROL_MASK);
/* glue drd init */
switch (mode) {
case USB_DR_MODE_PERIPHERAL:
clrbits_le32(syscfg_base + syscfg_offset,
USB3_DELAY_VBUSVALID | USB3_SEL_FORCE_OPMODE |
USB3_FORCE_OPMODE(0x3) | USB3_SEL_FORCE_DPPULLDOWN2 |
USB3_FORCE_DPPULLDOWN2 | USB3_SEL_FORCE_DMPULLDOWN2 |
USB3_FORCE_DMPULLDOWN2);
setbits_le32(syscfg_base + syscfg_offset,
USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID);
break;
case USB_DR_MODE_HOST:
clrbits_le32(syscfg_base + syscfg_offset,
USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID |
USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) |
USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 |
USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
setbits_le32(syscfg_base + syscfg_offset, USB3_DELAY_VBUSVALID);
break;
default:
dev_err(dev, "Unsupported mode of operation %d\n", mode);
return;
}
/* glue init */
setbits_le32(glue_base + CLKRST_CTRL, AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION);
clrbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
/* configure mux for vbus, powerpresent and bvalid signals */
setbits_le32(glue_base + USB2_VBUS_MNGMNT_SEL1,
SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG));
setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
};
struct dwc3_glue_ops stih407_ops = {
.glue_configure = dwc3_stih407_glue_configure,
};
static const struct udevice_id dwc3_sti_match[] = {
{ .compatible = "st,stih407-dwc3", .data = (ulong)&stih407_ops},
{ /* sentinel */ }
};
U_BOOT_DRIVER(dwc3_sti_wrapper) = {
.name = "dwc3-sti",
.id = UCLASS_NOP,
.of_match = dwc3_sti_match,
.bind = dwc3_glue_bind,
.probe = dwc3_glue_probe,
.remove = dwc3_glue_remove,
.plat_auto = sizeof(struct dwc3_glue_data),
};

26
drivers/usb/dwc3/dwc3-generic.c
View File

@@ -7,29 +7,17 @@
* Based on dwc3-omap.c.
*/
#include <cpu_func.h>
#include <log.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <generic-phy.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
#include <power/regulator.h>
#include <usb.h>
#include "core.h"
#include "gadget.h"
#include <reset.h>
#include <clk.h>
#include <usb/xhci.h>
#include <asm/gpio.h>
#include <dm/lists.h>
#include <linux/delay.h>
#include <linux/usb/gadget.h>
#include <power/regulator.h>
#include <usb/xhci.h>
#include "core.h"
#include "dwc3-generic.h"
#include "gadget.h"
struct dwc3_generic_plat {
fdt_addr_t base;

1
drivers/usb/gadget/f_mass_storage.c
View File

@@ -682,6 +682,7 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
schedule();
dm_usb_gadget_handle_interrupts(udcdev);
}
common->thread_wakeup_needed = 0;

3
drivers/usb/gadget/g_dnl.c
View File

@@ -207,7 +207,8 @@ void g_dnl_clear_detach(void)
static int on_serialno(const char *name, const char *value, enum env_op op,
int flags)
{
g_dnl_set_serialnumber((char *)value);
if (value)
g_dnl_set_serialnumber((char *)value);
return 0;
}
U_BOOT_ENV_CALLBACK(serialno, on_serialno);

9
drivers/usb/host/Kconfig
View File

@@ -110,15 +110,6 @@ config USB_XHCI_RCAR
Choose this option to add support for USB 3.0 driver on Renesas
R-Car Gen3 SoCs.
config USB_XHCI_STI
bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
depends on ARCH_STI
default y
help
Enables support for the on-chip xHCI controller on STMicroelectronics
STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic
to configure the controller.
config USB_XHCI_DRA7XX_INDEX
int "DRA7XX xHCI USB index"
range 0 1

1
drivers/usb/host/Makefile
View File

@@ -54,7 +54,6 @@ obj-$(CONFIG_USB_XHCI_GENERIC) += xhci-generic.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware

253
drivers/usb/host/dwc3-sti-glue.c
View File

@@ -1,253 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* STiH407 family DWC3 specific Glue layer
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <dm/lists.h>
#include <regmap.h>
#include <reset-uclass.h>
#include <syscon.h>
#include <usb.h>
#include <linux/printk.h>
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>
#include <dwc3-sti-glue.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
* @syscfg_base: addr for the glue syscfg
* @glue_base: addr for the glue registers
* @syscfg_offset: usb syscfg control offset
* @powerdown_ctl: rest controller for powerdown signal
* @softreset_ctl: reset controller for softreset signal
* @mode: drd static host/device config
*/
struct sti_dwc3_glue_plat {
phys_addr_t syscfg_base;
phys_addr_t glue_base;
phys_addr_t syscfg_offset;
struct reset_ctl powerdown_ctl;
struct reset_ctl softreset_ctl;
enum usb_dr_mode mode;
};
static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
{
unsigned long val;
val = readl(plat->syscfg_base + plat->syscfg_offset);
val &= USB3_CONTROL_MASK;
switch (plat->mode) {
case USB_DR_MODE_PERIPHERAL:
val &= ~(USB3_DELAY_VBUSVALID
| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
break;
case USB_DR_MODE_HOST:
val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
val |= USB3_DELAY_VBUSVALID;
break;
default:
pr_err("Unsupported mode of operation %d\n", plat->mode);
return -EINVAL;
}
writel(val, plat->syscfg_base + plat->syscfg_offset);
return 0;
}
static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
{
unsigned long reg;
reg = readl(plat->glue_base + CLKRST_CTRL);
reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
reg &= ~SW_PIPEW_RESET_N;
writel(reg, plat->glue_base + CLKRST_CTRL);
/* configure mux for vbus, powerpresent and bvalid signals */
reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
}
static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
{
struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
struct regmap *regmap;
int ret;
u32 reg[4];
ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg,
ARRAY_SIZE(reg));
if (ret) {
pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret);
return ret;
}
plat->glue_base = reg[0];
plat->syscfg_offset = reg[2];
/* get corresponding syscon phandle */
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg",
&syscon);
if (ret) {
pr_err("unable to find syscon device (%d)\n", ret);
return ret;
}
/* get syscfg-reg base address */
regmap = syscon_get_regmap(syscon);
if (!regmap) {
pr_err("unable to find regmap\n");
return -ENODEV;
}
plat->syscfg_base = regmap->ranges[0].start;
/* get powerdown reset */
ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl);
if (ret) {
pr_err("can't get powerdown reset for %s (%d)", dev->name, ret);
return ret;
}
/* get softreset reset */
ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl);
if (ret)
pr_err("can't get soft reset for %s (%d)", dev->name, ret);
return ret;
};
static int sti_dwc3_glue_bind(struct udevice *dev)
{
struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
ofnode node, dwc3_node;
/* Find snps,dwc3 node from subnode */
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
if (ofnode_device_is_compatible(node, "snps,dwc3"))
dwc3_node = node;
}
if (!ofnode_valid(dwc3_node)) {
pr_err("Can't find dwc3 subnode for %s\n", dev->name);
return -ENODEV;
}
/* retrieve the DWC3 dual role mode */
plat->mode = usb_get_dr_mode(dwc3_node);
if (plat->mode == USB_DR_MODE_UNKNOWN)
/* by default set dual role mode to HOST */
plat->mode = USB_DR_MODE_HOST;
return dm_scan_fdt_dev(dev);
}
static int sti_dwc3_glue_probe(struct udevice *dev)
{
struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
int ret;
/* deassert both powerdown and softreset */
ret = reset_deassert(&plat->powerdown_ctl);
if (ret < 0) {
pr_err("DWC3 powerdown reset deassert failed: %d", ret);
return ret;
}
ret = reset_deassert(&plat->softreset_ctl);
if (ret < 0) {
pr_err("DWC3 soft reset deassert failed: %d", ret);
goto softreset_err;
}
ret = sti_dwc3_glue_drd_init(plat);
if (ret)
goto init_err;
sti_dwc3_glue_init(plat);
return 0;
init_err:
ret = reset_assert(&plat->softreset_ctl);
if (ret < 0) {
pr_err("DWC3 soft reset deassert failed: %d", ret);
return ret;
}
softreset_err:
ret = reset_assert(&plat->powerdown_ctl);
if (ret < 0)
pr_err("DWC3 powerdown reset deassert failed: %d", ret);
return ret;
}
static int sti_dwc3_glue_remove(struct udevice *dev)
{
struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
int ret;
/* assert both powerdown and softreset */
ret = reset_assert(&plat->powerdown_ctl);
if (ret < 0) {
pr_err("DWC3 powerdown reset deassert failed: %d", ret);
return ret;
}
ret = reset_assert(&plat->softreset_ctl);
if (ret < 0)
pr_err("DWC3 soft reset deassert failed: %d", ret);
return ret;
}
static const struct udevice_id sti_dwc3_glue_ids[] = {
{ .compatible = "st,stih407-dwc3" },
{ }
};
U_BOOT_DRIVER(dwc3_sti_glue) = {
.name = "dwc3_sti_glue",
.id = UCLASS_NOP,
.of_match = sti_dwc3_glue_ids,
.of_to_plat = sti_dwc3_glue_of_to_plat,
.probe = sti_dwc3_glue_probe,
.remove = sti_dwc3_glue_remove,
.bind = sti_dwc3_glue_bind,
.plat_auto = sizeof(struct sti_dwc3_glue_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};

41
include/dwc3-sti-glue.h
View File

@@ -1,41 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#ifndef __DWC3_STI_UBOOT_H_
#define __DWC3_STI_UBOOT_H_
/* glue registers */
#include <linux/bitops.h>
#define CLKRST_CTRL 0x00
#define AUX_CLK_EN BIT(0)
#define SW_PIPEW_RESET_N BIT(4)
#define EXT_CFG_RESET_N BIT(8)
#define XHCI_REVISION BIT(12)
#define USB2_VBUS_MNGMNT_SEL1 0x2C
#define USB2_VBUS_UTMIOTG 0x1
#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0)
#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4)
#define SEL_OVERRIDE_BVALID(n) ((n) << 8)
/* Static DRD configuration */
#define USB3_CONTROL_MASK 0xf77
#define USB3_DEVICE_NOT_HOST BIT(0)
#define USB3_FORCE_VBUSVALID BIT(1)
#define USB3_DELAY_VBUSVALID BIT(2)
#define USB3_SEL_FORCE_OPMODE BIT(4)
#define USB3_FORCE_OPMODE(n) ((n) << 5)
#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8)
#define USB3_FORCE_DPPULLDOWN2 BIT(9)
#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10)
#define USB3_FORCE_DMPULLDOWN2 BIT(11)
int sti_dwc3_init(enum usb_dr_mode mode);
#endif /* __DWC3_STI_UBOOT_H_ */