Merge patch series "MediaTek MT7629 OF_UPSTREAM migration (v2)"
Weijie Gao <weijie.gao@mediatek.com> says: This patch series migrates MediaTek MT7629 to OF_UPSTREAM Changes in v2: * Remove mt7629-rfb.dtb from arch/arm/dts/Makefile * Add wdt-reboot node to make reset command work Link: https://lore.kernel.org/r/cover.1736851116.git.weijie.gao@mediatek.com
This commit is contained in:
Tom Rini
@@ -1181,7 +1181,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7623a-unielec-u7623-02-emmc.dtb \
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mt7622-bananapi-bpi-r64.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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mt7629-rfb.dtb \
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mt7981-rfb.dtb \
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mt7981-emmc-rfb.dtb \
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mt7981-sd-rfb.dtb \
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@@ -5,6 +5,59 @@
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <dt-bindings/reset/mt7629-reset.h>
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/ {
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dramc: dramc@10203000 {
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compatible = "mediatek,mt7629-dramc";
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reg = <0x10203000 0x600>, /* EMI */
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<0x10213000 0x1000>, /* DDRPHY */
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<0x10214000 0xd00>; /* DRAMC_AO */
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clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
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<&topckgen CLK_TOP_SYSPLL1_D8>,
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<&topckgen CLK_TOP_MEM_SEL>,
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<&topckgen CLK_TOP_DMPLL>;
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clock-names = "phy", "phy_mux", "mem", "mem_mux";
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};
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mcucfg: syscon@10200000 {
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compatible = "mediatek,mt7629-mcucfg", "syscon";
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reg = <0x10200000 0x1000>;
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#clock-cells = <1>;
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};
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timer0: timer@10004000 {
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
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<&topckgen CLK_TOP_10M_SEL>;
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clock-names = "mux", "src";
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};
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snand: snand@1100d000 {
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compatible = "mediatek,mt7629-snand";
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reg = <0x1100d000 0x1000>,
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<0x1100e000 0x1000>;
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reg-names = "nfi", "ecc";
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clocks = <&pericfg CLK_PERI_NFI_PD>,
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<&pericfg CLK_PERI_SNFI_PD>,
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<&pericfg CLK_PERI_NFIECC_PD>;
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clock-names = "nfi_clk", "pad_clk", "ecc_clk";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_NFI_INFRA_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL2_D8>;
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status = "disabled";
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&watchdog>;
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};
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};
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&infracfg {
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bootph-all;
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};
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@@ -35,8 +88,72 @@
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&uart0 {
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bootph-all;
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reg-shift = <2>;
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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};
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&snfi {
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&qspi {
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bootph-all;
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_pins>;
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status = "okay";
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/delete-node/ flash@0;
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spi-flash@0{
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bootph-all;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&pio {
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bootph-all;
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snfi_pins: snfi-pins {
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mux {
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bootph-all;
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function = "flash";
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groups = "snfi";
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};
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};
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snor_pins: snor-pins {
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mux {
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bootph-all;
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function = "flash";
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groups = "spi_nor";
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};
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};
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};
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&snand {
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pinctrl-names = "default";
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pinctrl-0 = <&snfi_pins>;
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status = "okay";
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quad-spi;
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bootph-all;
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};
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ð {
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resets = <ðsys ETHSYS_FE_RST>;
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reset-names = "fe";
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "2500base-x";
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mediatek,switch = "mt7531";
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reset-gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
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assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<&topckgen CLK_TOP_F10M_REF_SEL>,
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<&topckgen CLK_TOP_SGMII_REF_1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
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<&topckgen CLK_TOP_SYSPLL4_D16>,
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<&topckgen CLK_TOP_SGMIIPLL_D2>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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@@ -1,123 +0,0 @@
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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/dts-v1/;
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#include "mt7629.dtsi"
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#include "mt7629-rfb-u-boot.dtsi"
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/ {
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model = "MediaTek MT7629 RFB";
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compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
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aliases {
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spi0 = &snor;
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "2500base-x";
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mediatek,switch = "mt7531";
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reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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&pinctrl {
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state_default: pinmux_conf {
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bootph-all;
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mux {
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function = "jtag";
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groups = "ephy_leds_jtag";
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bootph-all;
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};
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};
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snfi_pins: snfi-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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};
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snor_pins: snor-pins {
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mux {
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function = "flash";
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groups = "spi_nor";
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};
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};
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uart0_pins: uart0-default {
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mux {
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function = "uart";
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groups = "uart0_txd_rxd";
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};
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};
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watchdog_pins: watchdog-default {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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};
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&snfi {
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pinctrl-names = "default", "snfi";
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pinctrl-0 = <&snor_pins>;
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pinctrl-1 = <&snfi_pins>;
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status = "disabled";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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bootph-all;
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};
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};
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&snor {
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pinctrl-names = "default";
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pinctrl-0 = <&snor_pins>;
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status = "okay";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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bootph-all;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&xhci {
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status = "okay";
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};
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&u3phy {
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status = "okay";
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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@@ -1,360 +0,0 @@
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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#include <dt-bindings/clock/mt7629-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt7629-power.h>
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#include <dt-bindings/reset/mt7629-reset.h>
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#include <dt-bindings/phy/phy.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "mediatek,mt7629";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clock-frequency = <1250000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clock-frequency = <1250000000>;
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};
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};
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clk20m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-output-names = "clk20m";
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};
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clk40m: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <20000000>;
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arm,cpu-registers-not-fw-configured;
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};
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infracfg: syscon@10000000 {
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compatible = "mediatek,mt7629-infracfg", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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pericfg: syscon@10002000 {
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compatible = "mediatek,mt7629-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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};
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timer0: timer@10004000 {
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
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<&topckgen CLK_TOP_10M_SEL>;
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clock-names = "mux", "src";
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7629-scpsys";
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reg = <0x10006000 0x1000>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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#power-domain-cells = <1>;
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infracfg = <&infracfg>;
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};
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mcucfg: syscon@10200000 {
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compatible = "mediatek,mt7629-mcucfg", "syscon";
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reg = <0x10200000 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,sysirq";
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reg = <0x10200a80 0x20>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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dramc: dramc@10203000 {
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compatible = "mediatek,mt7629-dramc";
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reg = <0x10203000 0x600>, /* EMI */
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<0x10213000 0x1000>, /* DDRPHY */
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<0x10214000 0xd00>; /* DRAMC_AO */
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clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
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<&topckgen CLK_TOP_SYSPLL1_D8>,
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<&topckgen CLK_TOP_MEM_SEL>,
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<&topckgen CLK_TOP_DMPLL>;
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clock-names = "phy", "phy_mux", "mem", "mem_mux";
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};
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apmixedsys: clock-controller@10209000 {
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compatible = "mediatek,mt7629-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: clock-controller@10210000 {
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compatible = "mediatek,mt7629-topckgen";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,wdt";
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reg = <0x10212000 0x600>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
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#reset-cells = <1>;
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status = "disabled";
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&watchdog>;
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};
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pinctrl: pinctrl@10217000 {
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compatible = "mediatek,mt7629-pinctrl";
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reg = <0x10217000 0x8000>;
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux_conf {
|
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};
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||||
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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||||
gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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};
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uart0: serial@11002000 {
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||||
compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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||||
reg-shift = <2>;
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||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
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<&pericfg CLK_PERI_UART0_PD>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
|
||||
};
|
||||
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uart1: serial@11003000 {
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||||
compatible = "mediatek,hsuart";
|
||||
reg = <0x11003000 0x400>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&pericfg CLK_PERI_UART1_PD>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,hsuart";
|
||||
reg = <0x11004000 0x400>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&pericfg CLK_PERI_UART2_PD>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
snfi: snfi@1100d000 {
|
||||
compatible = "mediatek,mtk-snfi-spi";
|
||||
reg = <0x1100d000 0x2000>;
|
||||
clocks = <&pericfg CLK_PERI_NFI_PD>,
|
||||
<&pericfg CLK_PERI_SNFI_PD>;
|
||||
clock-names = "nfi_clk", "pad_clk";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
|
||||
<&topckgen CLK_TOP_NFI_INFRA_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
|
||||
<&topckgen CLK_TOP_UNIVPLL2_D8>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
snor: snor@11014000 {
|
||||
compatible = "mediatek,mtk-snor";
|
||||
reg = <0x11014000 0x1000>;
|
||||
clocks = <&pericfg CLK_PERI_FLASH_PD>,
|
||||
<&topckgen CLK_TOP_FLASH_SEL>;
|
||||
clock-names = "spi", "sf";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ssusbsys: ssusbsys@1a000000 {
|
||||
compatible = "mediatek,mt7629-ssusbsys", "syscon";
|
||||
reg = <0x1a000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xhci: usb@1a0c0000 {
|
||||
compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
|
||||
reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
|
||||
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
|
||||
<&ssusbsys CLK_SSUSB_REF_EN>,
|
||||
<&ssusbsys CLK_SSUSB_MCU_EN>,
|
||||
<&ssusbsys CLK_SSUSB_DMA_EN>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
||||
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u3phy: usb-phy@1a0c4000 {
|
||||
compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1a0c4000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0x0 0x0700>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
u3port0: usb-phy@700 {
|
||||
reg = <0x0700 0x0700>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@1b000000 {
|
||||
compatible = "mediatek,mt7629-ethsys", "syscon";
|
||||
reg = <0x1b000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
eth: ethernet@1b100000 {
|
||||
compatible = "mediatek,mt7629-eth", "syscon";
|
||||
reg = <0x1b100000 0x20000>;
|
||||
clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
||||
<&topckgen CLK_TOP_F10M_REF_SEL>,
|
||||
<ðsys CLK_ETH_ESW_EN>,
|
||||
<ðsys CLK_ETH_GP0_EN>,
|
||||
<ðsys CLK_ETH_GP1_EN>,
|
||||
<ðsys CLK_ETH_GP2_EN>,
|
||||
<ðsys CLK_ETH_FE_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_TX_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_RX_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_CDR_REF>,
|
||||
<&sgmiisys0 CLK_SGMII_CDR_FB>,
|
||||
<&sgmiisys1 CLK_SGMII_TX_EN>,
|
||||
<&sgmiisys1 CLK_SGMII_RX_EN>,
|
||||
<&sgmiisys1 CLK_SGMII_CDR_REF>,
|
||||
<&sgmiisys1 CLK_SGMII_CDR_FB>,
|
||||
<&apmixedsys CLK_APMIXED_SGMIPLL>,
|
||||
<&apmixedsys CLK_APMIXED_ETH2PLL>;
|
||||
clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
|
||||
"fe", "sgmii_tx250m", "sgmii_rx250m",
|
||||
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||
"sgmii_ck", "eth2pll";
|
||||
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
||||
<&topckgen CLK_TOP_F10M_REF_SEL>,
|
||||
<&topckgen CLK_TOP_SGMII_REF_1_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
|
||||
<&topckgen CLK_TOP_SYSPLL4_D16>,
|
||||
<&topckgen CLK_TOP_SGMIIPLL_D2>;
|
||||
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
|
||||
resets = <ðsys ETHSYS_FE_RST>;
|
||||
reset-names = "fe";
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@1b128000 {
|
||||
compatible = "mediatek,mt7629-sgmiisys", "syscon";
|
||||
reg = <0x1b128000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sgmiisys1: syscon@1b130000 {
|
||||
compatible = "mediatek,mt7629-sgmiisys", "syscon";
|
||||
reg = <0x1b130000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pwm: pwm@11006000 {
|
||||
compatible = "mediatek,mt7629-pwm";
|
||||
reg = <0x11006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#pwm-cells = <2>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
||||
<&pericfg CLK_PERI_PWM_PD>,
|
||||
<&pericfg CLK_PERI_PWM1_PD>;
|
||||
clock-names = "top", "main", "pwm1";
|
||||
assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41fffef0
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt7629-rfb"
|
||||
CONFIG_TARGET_MT7629=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
@@ -52,6 +52,7 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-parents"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
|
||||
@@ -574,6 +574,18 @@ static const struct mtk_clk_tree mt7629_clk_tree = {
|
||||
.muxes = top_muxes,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_tree mt7629_peri_clk_tree = {
|
||||
.xtal_rate = 40 * MHZ,
|
||||
.xtal2_rate = 20 * MHZ,
|
||||
.gates_offs = CLK_PERI_PWM1_PD,
|
||||
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
|
||||
.muxes_offs = CLK_TOP_AXI_SEL,
|
||||
.plls = apmixed_plls,
|
||||
.fclks = top_fixed_clks,
|
||||
.fdivs = top_fixed_divs,
|
||||
.muxes = top_muxes,
|
||||
};
|
||||
|
||||
static int mt7629_mcucfg_probe(struct udevice *dev)
|
||||
{
|
||||
void __iomem *base;
|
||||
@@ -619,7 +631,7 @@ static int mt7629_infracfg_probe(struct udevice *dev)
|
||||
|
||||
static int mt7629_pericfg_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
|
||||
return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs);
|
||||
}
|
||||
|
||||
static int mt7629_ethsys_probe(struct udevice *dev)
|
||||
|
||||
@@ -1,206 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT7629_H
|
||||
#define _DT_BINDINGS_CLK_MT7629_H
|
||||
|
||||
/* TOPCKGEN */
|
||||
#define CLK_TOP_FCLKS_OFF 0
|
||||
|
||||
#define CLK_TOP_TO_U2_PHY 0
|
||||
#define CLK_TOP_TO_U2_PHY_1P 1
|
||||
#define CLK_TOP_PCIE0_PIPE_EN 2
|
||||
#define CLK_TOP_PCIE1_PIPE_EN 3
|
||||
#define CLK_TOP_SSUSB_TX250M 4
|
||||
#define CLK_TOP_SSUSB_EQ_RX250M 5
|
||||
#define CLK_TOP_SSUSB_CDR_REF 6
|
||||
#define CLK_TOP_SSUSB_CDR_FB 7
|
||||
#define CLK_TOP_SATA_ASIC 8
|
||||
#define CLK_TOP_SATA_RBC 9
|
||||
|
||||
#define CLK_TOP_TO_USB3_SYS 10
|
||||
#define CLK_TOP_P1_1MHZ 11
|
||||
#define CLK_TOP_4MHZ 12
|
||||
#define CLK_TOP_P0_1MHZ 13
|
||||
#define CLK_TOP_ETH_500M 14
|
||||
#define CLK_TOP_TXCLK_SRC_PRE 15
|
||||
#define CLK_TOP_RTC 16
|
||||
#define CLK_TOP_PWM_QTR_26M 17
|
||||
#define CLK_TOP_CPUM_TCK_IN 18
|
||||
#define CLK_TOP_TO_USB3_DA_TOP 19
|
||||
#define CLK_TOP_MEMPLL 20
|
||||
#define CLK_TOP_DMPLL 21
|
||||
#define CLK_TOP_DMPLL_D4 22
|
||||
#define CLK_TOP_DMPLL_D8 23
|
||||
#define CLK_TOP_SYSPLL_D2 24
|
||||
#define CLK_TOP_SYSPLL1_D2 25
|
||||
#define CLK_TOP_SYSPLL1_D4 26
|
||||
#define CLK_TOP_SYSPLL1_D8 27
|
||||
#define CLK_TOP_SYSPLL1_D16 28
|
||||
#define CLK_TOP_SYSPLL2_D2 29
|
||||
#define CLK_TOP_SYSPLL2_D4 30
|
||||
#define CLK_TOP_SYSPLL2_D8 31
|
||||
#define CLK_TOP_SYSPLL_D5 32
|
||||
#define CLK_TOP_SYSPLL3_D2 33
|
||||
#define CLK_TOP_SYSPLL3_D4 34
|
||||
#define CLK_TOP_SYSPLL_D7 35
|
||||
#define CLK_TOP_SYSPLL4_D2 36
|
||||
#define CLK_TOP_SYSPLL4_D4 37
|
||||
#define CLK_TOP_SYSPLL4_D16 38
|
||||
#define CLK_TOP_UNIVPLL 39
|
||||
#define CLK_TOP_UNIVPLL1_D2 40
|
||||
#define CLK_TOP_UNIVPLL1_D4 41
|
||||
#define CLK_TOP_UNIVPLL1_D8 42
|
||||
#define CLK_TOP_UNIVPLL_D3 43
|
||||
#define CLK_TOP_UNIVPLL2_D2 44
|
||||
#define CLK_TOP_UNIVPLL2_D4 45
|
||||
#define CLK_TOP_UNIVPLL2_D8 46
|
||||
#define CLK_TOP_UNIVPLL2_D16 47
|
||||
#define CLK_TOP_UNIVPLL_D5 48
|
||||
#define CLK_TOP_UNIVPLL3_D2 49
|
||||
#define CLK_TOP_UNIVPLL3_D4 50
|
||||
#define CLK_TOP_UNIVPLL3_D16 51
|
||||
#define CLK_TOP_UNIVPLL_D7 52
|
||||
#define CLK_TOP_UNIVPLL_D80_D4 53
|
||||
#define CLK_TOP_UNIV48M 54
|
||||
#define CLK_TOP_SGMIIPLL_D2 55
|
||||
#define CLK_TOP_CLKXTAL_D4 56
|
||||
#define CLK_TOP_HD_FAXI 57
|
||||
#define CLK_TOP_FAXI 58
|
||||
#define CLK_TOP_F_FAUD_INTBUS 59
|
||||
#define CLK_TOP_AP2WBHIF_HCLK 60
|
||||
#define CLK_TOP_10M_INFRAO 61
|
||||
#define CLK_TOP_MSDC30_1 62
|
||||
#define CLK_TOP_SPI 63
|
||||
#define CLK_TOP_SF 64
|
||||
#define CLK_TOP_FLASH 65
|
||||
#define CLK_TOP_TO_USB3_REF 66
|
||||
#define CLK_TOP_TO_USB3_MCU 67
|
||||
#define CLK_TOP_TO_USB3_DMA 68
|
||||
#define CLK_TOP_FROM_TOP_AHB 69
|
||||
#define CLK_TOP_FROM_TOP_AXI 70
|
||||
#define CLK_TOP_PCIE1_MAC_EN 71
|
||||
#define CLK_TOP_PCIE0_MAC_EN 72
|
||||
|
||||
#define CLK_TOP_AXI_SEL 73
|
||||
#define CLK_TOP_MEM_SEL 74
|
||||
#define CLK_TOP_DDRPHYCFG_SEL 75
|
||||
#define CLK_TOP_ETH_SEL 76
|
||||
#define CLK_TOP_PWM_SEL 77
|
||||
#define CLK_TOP_F10M_REF_SEL 78
|
||||
#define CLK_TOP_NFI_INFRA_SEL 79
|
||||
#define CLK_TOP_FLASH_SEL 80
|
||||
#define CLK_TOP_UART_SEL 81
|
||||
#define CLK_TOP_SPI0_SEL 82
|
||||
#define CLK_TOP_SPI1_SEL 83
|
||||
#define CLK_TOP_MSDC50_0_SEL 84
|
||||
#define CLK_TOP_MSDC30_0_SEL 85
|
||||
#define CLK_TOP_MSDC30_1_SEL 86
|
||||
#define CLK_TOP_AP2WBMCU_SEL 87
|
||||
#define CLK_TOP_AP2WBHIF_SEL 88
|
||||
#define CLK_TOP_AUDIO_SEL 89
|
||||
#define CLK_TOP_AUD_INTBUS_SEL 90
|
||||
#define CLK_TOP_PMICSPI_SEL 91
|
||||
#define CLK_TOP_SCP_SEL 92
|
||||
#define CLK_TOP_ATB_SEL 93
|
||||
#define CLK_TOP_HIF_SEL 94
|
||||
#define CLK_TOP_SATA_SEL 95
|
||||
#define CLK_TOP_U2_SEL 96
|
||||
#define CLK_TOP_AUD1_SEL 97
|
||||
#define CLK_TOP_AUD2_SEL 98
|
||||
#define CLK_TOP_IRRX_SEL 99
|
||||
#define CLK_TOP_IRTX_SEL 100
|
||||
#define CLK_TOP_SATA_MCU_SEL 101
|
||||
#define CLK_TOP_PCIE0_MCU_SEL 102
|
||||
#define CLK_TOP_PCIE1_MCU_SEL 103
|
||||
#define CLK_TOP_SSUSB_MCU_SEL 104
|
||||
#define CLK_TOP_CRYPTO_SEL 105
|
||||
#define CLK_TOP_SGMII_REF_1_SEL 106
|
||||
#define CLK_TOP_10M_SEL 107
|
||||
#define CLK_TOP_NR_CLK 108
|
||||
|
||||
/* INFRACFG */
|
||||
#define CLK_INFRA_MUX1_SEL 0
|
||||
#define CLK_INFRA_DBGCLK_PD 1
|
||||
#define CLK_INFRA_TRNG_PD 2
|
||||
#define CLK_INFRA_DEVAPC_PD 3
|
||||
#define CLK_INFRA_APXGPT_PD 4
|
||||
#define CLK_INFRA_SEJ_PD 5
|
||||
#define CLK_INFRA_NR_CLK 6
|
||||
|
||||
/* PERICFG */
|
||||
#define CLK_PERIBUS_SEL 0
|
||||
#define CLK_PERI_PWM1_PD 1
|
||||
#define CLK_PERI_PWM2_PD 2
|
||||
#define CLK_PERI_PWM3_PD 3
|
||||
#define CLK_PERI_PWM4_PD 4
|
||||
#define CLK_PERI_PWM5_PD 5
|
||||
#define CLK_PERI_PWM6_PD 6
|
||||
#define CLK_PERI_PWM7_PD 7
|
||||
#define CLK_PERI_PWM_PD 8
|
||||
#define CLK_PERI_AP_DMA_PD 9
|
||||
#define CLK_PERI_MSDC30_1_PD 10
|
||||
#define CLK_PERI_UART0_PD 11
|
||||
#define CLK_PERI_UART1_PD 12
|
||||
#define CLK_PERI_UART2_PD 13
|
||||
#define CLK_PERI_UART3_PD 14
|
||||
#define CLK_PERI_BTIF_PD 15
|
||||
#define CLK_PERI_I2C0_PD 16
|
||||
#define CLK_PERI_SPI0_PD 17
|
||||
#define CLK_PERI_SNFI_PD 18
|
||||
#define CLK_PERI_NFI_PD 19
|
||||
#define CLK_PERI_NFIECC_PD 20
|
||||
#define CLK_PERI_FLASH_PD 21
|
||||
#define CLK_PERI_NR_CLK 22
|
||||
|
||||
/* APMIXEDSYS */
|
||||
#define CLK_APMIXED_ARMPLL 0
|
||||
#define CLK_APMIXED_MAINPLL 1
|
||||
#define CLK_APMIXED_UNIV2PLL 2
|
||||
#define CLK_APMIXED_ETH1PLL 3
|
||||
#define CLK_APMIXED_ETH2PLL 4
|
||||
#define CLK_APMIXED_SGMIPLL 5
|
||||
#define CLK_APMIXED_NR_CLK 6
|
||||
|
||||
/* SSUSBSYS */
|
||||
#define CLK_SSUSB_U2_PHY_1P_EN 0
|
||||
#define CLK_SSUSB_U2_PHY_EN 1
|
||||
#define CLK_SSUSB_REF_EN 2
|
||||
#define CLK_SSUSB_SYS_EN 3
|
||||
#define CLK_SSUSB_MCU_EN 4
|
||||
#define CLK_SSUSB_DMA_EN 5
|
||||
#define CLK_SSUSB_NR_CLK 6
|
||||
|
||||
/* PCIESYS */
|
||||
#define CLK_PCIE_P1_AUX_EN 0
|
||||
#define CLK_PCIE_P1_OBFF_EN 1
|
||||
#define CLK_PCIE_P1_AHB_EN 2
|
||||
#define CLK_PCIE_P1_AXI_EN 3
|
||||
#define CLK_PCIE_P1_MAC_EN 4
|
||||
#define CLK_PCIE_P1_PIPE_EN 5
|
||||
#define CLK_PCIE_P0_AUX_EN 6
|
||||
#define CLK_PCIE_P0_OBFF_EN 7
|
||||
#define CLK_PCIE_P0_AHB_EN 8
|
||||
#define CLK_PCIE_P0_AXI_EN 9
|
||||
#define CLK_PCIE_P0_MAC_EN 10
|
||||
#define CLK_PCIE_P0_PIPE_EN 11
|
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#define CLK_PCIE_NR_CLK 12
|
||||
|
||||
/* ETHSYS */
|
||||
#define CLK_ETH_FE_EN 0
|
||||
#define CLK_ETH_GP2_EN 1
|
||||
#define CLK_ETH_GP1_EN 2
|
||||
#define CLK_ETH_GP0_EN 3
|
||||
#define CLK_ETH_ESW_EN 4
|
||||
#define CLK_ETH_NR_CLK 5
|
||||
|
||||
/* SGMIISYS */
|
||||
#define CLK_SGMII_TX_EN 0
|
||||
#define CLK_SGMII_RX_EN 1
|
||||
#define CLK_SGMII_CDR_REF 2
|
||||
#define CLK_SGMII_CDR_FB 3
|
||||
#define CLK_SGMII_NR_CLK 4
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT7629_H */
|
||||
Reference in New Issue
Block a user