doc: board: ti: k3: Add J784S4 EVM and AM69 SK documentation
TI K3 J784S4 and AM69 are new additions to the K3 SoC family. Add documentation about the J784S4 EVM and AM69 SK. Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
This commit is contained in:
Apurva Nandan
@@ -10,6 +10,7 @@ F: arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
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F: arch/arm/dts/k3-j784s4-r5-evm.dts
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F: arch/arm/dts/k3-j784s4-ddr.dtsi
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F: arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
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F: doc/board/ti/j784s4_evm.rst
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AM69 SK BOARD
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M: Apurva Nandan <a-nandan@ti.com>
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299
doc/board/ti/j784s4_evm.rst
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299
doc/board/ti/j784s4_evm.rst
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.. SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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.. sectionauthor:: Apurva Nandan <a-nandan@ti.com>
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J784S4 and AM69 Platforms
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=========================
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Introduction
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------------
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The J784S4 SoC belongs to the K3 Multicore SoC architecture
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platform, providing advanced system integration in automotive,
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ADAS and industrial applications requiring AI at the network edge.
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This SoC extends the K3 Jacinto 7 family of SoCs with focus on
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raising performance and integration while providing interfaces,
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memory architecture and compute performance for multi-sensor, high
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concurrency applications.
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The device is partitioned into three functional domains, each containing
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specific processing cores and peripherals:
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1. Wake-up (WKUP) domain
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* ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
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2. Microcontroller (MCU) domain
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* Dual core ARM Cortex-R5F processor, runs device management
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and SoC early boot
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3. MAIN domain
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* Two clusters of quad core 64-bit ARM Cortex-A72, runs HLOS
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* Dual core ARM Cortex-R5F processor used for RTOS applications
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* Four C7x DSPs used for Machine Learning applications.
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More info can be found in TRM: http://www.ti.com/lit/zip/spruj52
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Platform information:
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* https://www.ti.com/tool/J784S4XEVM
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* https://www.ti.com/tool/SK-AM69
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Boot Flow
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---------
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Below is the pictorial representation of boot flow:
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.. image:: img/boot_diagram_k3_current.svg
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:alt: K3 boot flow
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- On this platform, "TI Foundational Security" (TIFS) functions as the
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security enclave master. While "Device Manager" (DM), also known as the
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"TISCI server" in TI terminology, offers all the essential services.
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- As illustrated in the diagram above, R5 SPL manages power and clock
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services independently before handing over control to DM. The A72 or
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the C7x (Aux core) software components request TIFS/DM to handle
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security or device management services.
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Sources
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-------
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_boot_sources
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:end-before: .. k3_rst_include_end_boot_sources
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Build procedure
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---------------
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0. Setup the environment variables:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_common_env_vars_desc
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:end-before: .. k3_rst_include_end_common_env_vars_desc
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_board_env_vars_desc
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:end-before: .. k3_rst_include_end_board_env_vars_desc
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Set the variables corresponding to this platform:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_common_env_vars_defn
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:end-before: .. k3_rst_include_end_common_env_vars_defn
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.. code-block:: bash
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$ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig
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$ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig
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$ export TFA_BOARD=j784s4
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$ export TFA_EXTRA_ARGS="K3_USART=0x8"
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$ export OPTEE_PLATFORM=k3-j784s4
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$ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
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.. j784s4_evm_rst_include_start_build_steps
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1. Trusted Firmware-A
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_tfa
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:end-before: .. k3_rst_include_end_build_steps_tfa
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2. OP-TEE
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_optee
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:end-before: .. k3_rst_include_end_build_steps_optee
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3. U-Boot
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.. _j784s4_evm_rst_u_boot_r5:
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* 3.1 R5
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_spl_r5
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:end-before: .. k3_rst_include_end_build_steps_spl_r5
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.. _j784s4_evm_rst_u_boot_a72:
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* 3.2 A72
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_uboot
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:end-before: .. k3_rst_include_end_build_steps_uboot
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.. j784s4_evm_rst_include_end_build_steps
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Target Images
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-------------
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In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
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variant (GP, HS-FS, HS-SE) requires a different source for these files.
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- GP
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* tiboot3-j784s4-gp-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
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* tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
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- HS-FS
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* tiboot3-j784s4-hs-fs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
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* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
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- HS-SE
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* tiboot3-j784s4-hs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
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* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
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Image formats
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-------------
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- tiboot3.bin
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.. image:: img/multi_cert_tiboot3.bin.svg
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:alt: tiboot3.bin format
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- tispl.bin
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.. image:: img/dm_tispl.bin.svg
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:alt: tispl.bin format
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R5 Memory Map
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-------------
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.. list-table::
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:widths: 16 16 16
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:header-rows: 1
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* - Region
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- Start Address
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- End Address
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* - SPL
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- 0x41c00000
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- 0x41c40000
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* - EMPTY
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- 0x41c40000
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- 0x41c61f20
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* - STACK
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- 0x41c65f20
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- 0x41c61f20
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* - Global data
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- 0x41c65f20
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- 0x41c66000
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* - Heap
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- 0x41c66000
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- 0x41c76000
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* - BSS
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- 0x41c76000
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- 0x41c80000
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* - DM DATA
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- 0x41c80000
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- 0x41c84130
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* - EMPTY
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- 0x41c84130
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- 0x41cff9fc
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* - MCU Scratchpad
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- 0x41cff9fc
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- 0x41cffbfc
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* - ROM DATA
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- 0x41cffbfc
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- 0x41cfffff
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Switch Setting for Boot Mode
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----------------------------
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Boot Mode pins provide means to select the boot mode and options before the
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device is powered up. After every POR, they are the main source to populate
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the Boot Parameter Tables.
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Boot Mode Pins for J784S4-EVM
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following tables show some common boot modes used on J784S4 EVM platform.
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More details can be found in the Technical Reference Manual:
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http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section.
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.. list-table:: J784S4 EVM Boot Modes
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:widths: 16 16 16
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:header-rows: 1
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* - Switch Label
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- SW11: 12345678
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- SW7: 12345678
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* - SD
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- 10000010
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- 00000000
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* - EMMC
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- 10000000
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- 01000000
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* - OSPI
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- 00000110
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- 01000000
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* - UART
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- 00000000
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- 01110000
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For SW7 and SW11, the switch state in the "ON" position = 1.
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Boot Mode Pins for AM69-SK
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following table show some common boot modes used on AM69-SK platform.
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More details can be found in the User Guide for AM69-SK:
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https://www.ti.com/lit/ug/spruj70/spruj70.pdf under the `Bootmode Settings`
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section.
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.. list-table:: AM69 SK Boot Modes
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:widths: 16 16
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:header-rows: 1
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* - Switch Label
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- SW2: 1234
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* - SD
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- 0000
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* - EMMC
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- 0110
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* - UART
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- 1010
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For SW2, the switch state in the "ON" position = 1.
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Debugging U-Boot
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----------------
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See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
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detailed setup information.
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.. warning::
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**OpenOCD support since**: September 2023 (git master)
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Until the next stable release of OpenOCD is available in your development
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environment's distribution, it might be necessary to build OpenOCD `from the
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source <https://github.com/openocd-org/openocd>`_.
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Debugging U-Boot on J784S4-EVM and AM69-SK
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_openocd_connect_XDS110
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:end-before: .. k3_rst_include_end_openocd_connect_XDS110
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To start OpenOCD and connect to J784S4-EVM or AM69-SK board, use the
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following.
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.. code-block:: bash
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openocd -f board/ti_j784s4evm.cfg
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@@ -41,6 +41,7 @@ K3 Based SoCs
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../beagle/j721e_beagleboneai64
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j721e_evm
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j721s2_evm
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j784s4_evm
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Boot Flow Overview
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------------------
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