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imx: imx93_evk: Add basic board support

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Add basic board codes and defconfig for i.MX93 11x11 EVK board.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
2022-07-26 16:41:10 +08:00
committed by Stefano Babic
parent 0da3d96e10
commit 86a179703c
13 changed files with 2659 additions and 1 deletions
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3
arch/arm/dts/Makefile
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@@ -971,6 +971,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-evk.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb

157
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi Normal file
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@@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
u-boot,dm-spl;
};
aliases {
usbgadget0 = &usbg1;
usbgadget1 = &usbg2;
};
usbg1: usbg1 {
compatible = "fsl,imx27-usb-gadget";
dr_mode = "peripheral";
chipidea,usb = <&usbotg1>;
status = "okay";
};
usbg2: usbg2 {
compatible = "fsl,imx27-usb-gadget";
dr_mode = "peripheral";
chipidea,usb = <&usbotg2>;
status = "okay";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
u-boot,dm-spl;
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&lpuart1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c2 {
u-boot,dm-spl;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
u-boot,dm-spl;
};
&pinctrl_lpi2c2 {
u-boot,dm-spl;
};
&fec {
phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&eqos {
compatible = "fsl,imx-eqos";
};
&ethphy1 {
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&usbotg1 {
status = "okay";
extcon = <&ptn5110>;
};
&usbotg2 {
status = "okay";
extcon = <&ptn5110_2>;
};
&s4muap {
u-boot,dm-spl;
status = "okay";
};

527
arch/arm/dts/imx93-11x11-evk.dts Normal file
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@@ -0,0 +1,527 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
/dts-v1/;
#include "imx93.dtsi"
/{
chosen {
stdout-path = &lpuart1;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
audio: audio@a4120000 {
compatible = "shared-dma-pool";
reg = <0 0xa4120000 0 0x100000>;
no-map;
};
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
regulator-name = "can2-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
enable-active-low;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&lpi2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
reg = <0x50>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
ptn5110_2: tcpc@51 {
compatible = "nxp,ptn5110";
reg = <0x51>;
interrupt-parent = <&pcal6524>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
port {
typec2_dr_sw: endpoint {
remote-endpoint = <&usb2_drd_sw>;
};
};
typec2_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
interrupt-parent = <&pcal6524>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6524>;
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
adp5585gpio: gpio@34 {
compatible = "adp5585";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
};
&lpuart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
no-sdio;
no-mmc;
};
&usdhc3 {
status = "disabled";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
eee-broken-1000t;
rtl821x,aldps-disable;
rtl821x,clkout-disable;
};
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
rtl821x,aldps-disable;
rtl821x,clkout-disable;
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "disabled";
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&iomuxc {
pinctrl-names = "default";
status = "okay";
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42
MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42
MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42
MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42
MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42
MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42
MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42
MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42
MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42
MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42
MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42
MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};
&wdog3 {
status = "okay";
};

13
arch/arm/mach-imx/imx9/Kconfig
View File

@@ -18,4 +18,17 @@ config IMX93
config SYS_SOC
default "imx9"
choice
prompt "NXP i.MX9 board select"
optional
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
select IMX93
endchoice
source "board/freescale/imx93_evk/Kconfig"
endif

2
board/freescale/common/Makefile
View File

@@ -65,7 +65,7 @@ obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
ifneq (,$(filter $(SOC), imx8ulp))
ifneq (,$(filter $(SOC), imx8ulp imx9))
obj-y += mmc.o
endif

19
board/freescale/imx93_evk/Kconfig Normal file
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@@ -0,0 +1,19 @@
if TARGET_IMX93_11X11_EVK
config SYS_BOARD
default "imx93_evk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx93_evk"
config IMX93_EVK_LPDDR4X
bool "Using LPDDR4X Timing and PMIC voltage"
default y
select IMX9_LPDDR4X
help
Select the LPDDR4X timing and 0.6V VDDQ
endif

6
board/freescale/imx93_evk/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
i.MX93 MEK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx93_evk/
F: include/configs/imx93_evk.h
F: configs/imx93_11x11_evk_defconfig

12
board/freescale/imx93_evk/Makefile Normal file
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@@ -0,0 +1,12 @@
#
# Copyright 2022 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
endif

57
board/freescale/imx93_evk/imx93_evk.c Normal file
View File

@@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/arch-imx9/ccm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx9/imx93_pins.h>
#include <asm/arch/clock.h>
#include <power/pmic.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <usb.h>
#include <dwc3-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(LPUART1_CLK_ROOT);
return 0;
}
int board_init(void)
{
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "11X11_EVK");
env_set("board_rev", "iMX93");
#endif
return 0;
}

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board/freescale/imx93_evk/lpddr4x_timing.c Normal file
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126
board/freescale/imx93_evk/spl.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx93_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/mach-imx/s400_api.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <linux/delay.h>
#include <asm/arch/clock.h>
#include <asm/arch/ccm_regs.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <asm/arch/trdc.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_board_init(void)
{
puts("Normal Boot\n");
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
puts("No pca9450@25\n");
return 0;
}
if (ret != 0)
return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* 0.9v
*/
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
#endif
extern int imx9_probe_mu(void *ctx, struct event *event);
void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
timer_init();
arch_cpu_init();
board_early_init_f();
spl_early_init();
preloader_console_init();
ret = imx9_probe_mu(NULL, NULL);
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
printf("SOC: 0x%x\n", gd->arch.soc_rev);
printf("LC: 0x%x\n", gd->arch.lifecycle);
}
power_init_board();
/* Init power of mix */
soc_power_init();
/* Setup TRDC for DDR access */
trdc_init();
/* DDR initialization */
spl_dram_init();
/* Put M33 into CPUWAIT for following kick */
ret = m33_prepare();
if (!ret)
printf("M33 prepare ok\n");
board_init_r(NULL, 0);
}

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configs/imx93_11x11_evk_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARCH_IMX9=y
CONFIG_SYS_TEXT_BASE=0x80200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_TARGET_IMX93_11X11_EVK=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2051e000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x2051ddd0
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_SYS_I2C_SPEED=100000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
CONFIG_DM_PMIC=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_ULP_WATCHDOG=y
CONFIG_LZO=y
CONFIG_BZIP2=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth0"

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2022 NXP
*/
#ifndef __IMX93_EVK_H
#define __IMX93_EVK_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_MALLOC_F_ADDR 0x204D0000
#endif
#ifdef CONFIG_DISTRO_DEFAULTS
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
#include <config_distro_bootcmd.h>
#else
#define BOOTENV
#endif
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
"scriptaddr=0x83500000\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"splashimage=0x90000000\0" \
"console=ttyLP0,115200 earlycon\0" \
"fdt_addr_r=0x83000000\0" \
"fdt_addr=0x83000000\0" \
"cntr_addr=0x98000000\0" \
"cntr_file=os_cntr_signed.bin\0" \
"boot_fit=no\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
"auth_os=auth_cntr ${cntr_addr}\0" \
"boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${sec_boot} = yes; then " \
"if run auth_os; then " \
"run boot_os; " \
"else " \
"echo ERR: failed to authenticate; " \
"fi; " \
"else " \
"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
"bootm ${loadaddr}; " \
"else " \
"if run loadfdt; then " \
"run boot_os; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi;" \
"fi;\0" \
"netargs=setenv bootargs ${jh_clk} console=${console} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"if test ${sec_boot} = yes; then " \
"${get_cmd} ${cntr_addr} ${cntr_file}; " \
"if run auth_os; then " \
"run boot_os; " \
"else " \
"echo ERR: failed to authenticate; " \
"fi; " \
"else " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
"bootm ${loadaddr}; " \
"else " \
"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
"run boot_os; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi;" \
"fi;\0" \
"bsp_bootcmd=echo Running BSP bootcmd ...; " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if test ${sec_boot} = yes; then " \
"if run loadcntr; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"fi; " \
"fi;"
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#if defined(CONFIG_CMD_NET)
#define DWC_NET_PHYADDR 1
#define PHY_ANEG_TIMEOUT 20000
#endif
#endif