board/BuR/zynq: initial commit
This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170 boards. This boards are based on the Xilinx Zynq SoC. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20250404072819.69642-5-bernhard.messerklinger@br-automation.com Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Bernhard Messerklinger
committed by
Michal Simek
Michal Simek
parent
80e9b279a3
commit
8e25e76fff
@@ -303,6 +303,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
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zynqmp-zc1751-xm017-dc3.dtb \
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zynqmp-zc1751-xm018-dc4.dtb \
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zynqmp-zc1751-xm019-dc5.dtb
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dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
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zynq-brcp1_2r.dtb \
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zynq-brcp1_1r.dtb \
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zynq-brcp1_1r_switch.dtb \
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zynq-brsmarc2.dtb \
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zynq-brcp150.dtb \
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zynq-brcp170.dtb
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zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
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zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
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102
arch/arm/dts/zynq-binman-brcp1.dtsi
Normal file
102
arch/arm/dts/zynq-binman-brcp1.dtsi
Normal file
@@ -0,0 +1,102 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 B&R Industrial Automation GmbH
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*/
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#include <config.h>
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/ {
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binman {
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bootph-all;
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filename = "flash.bin";
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pad-byte = <0xff>;
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align-size = <16>;
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align = <16>;
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blob@0 {
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filename = "spl/boot.bin";
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offset = <0x0>;
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};
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fit {
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description = "U-Boot BR Zynq boards";
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offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
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images {
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uboot {
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description = "U-Boot BR Zynq";
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type = "firmware";
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os = "u-boot";
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arch = "arm";
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compression = "none";
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load = <CONFIG_TEXT_BASE>;
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u-boot-nodtb {
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};
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};
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fdt-0 {
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description = "DTB BR Zynq";
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type = "flat_dt";
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arch = "arm";
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compression = "none";
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u-boot-dtb {
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};
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};
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};
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configurations {
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default = "conf-0";
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conf-0 {
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description = "BR Zynq";
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firmware = "uboot";
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fdt = "fdt-0";
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};
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};
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};
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blob-ext@0 {
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filename = "blobs/cfg.img";
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offset = <0xC0000>;
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size = <0x10000>;
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optional;
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};
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blob-ext@5 {
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filename = "blobs/cfg_opt.img";
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offset = <0xD0000>;
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size = <0x10000>;
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optional;
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};
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blob-ext@1 {
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bootph-all;
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filename = "blobs/bitstream.bit";
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offset = <0x100000>;
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size = <0x200000>;
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optional;
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};
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blob-ext@4 {
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bootph-all;
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filename = "blobs/bitstream_update.bit";
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offset = <0x400000>;
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size = <0x200000>;
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optional;
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};
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blob-ext@2 {
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filename = "blobs/bootar.itb";
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offset = <0x900000>;
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size = <0x600000>;
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optional;
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};
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blob-ext@3 {
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filename = "blobs/dtb.bin";
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offset = <0xF00000>;
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size = <0x100000>;
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optional;
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};
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};
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};
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131
arch/arm/dts/zynq-brcp1.dtsi
Normal file
131
arch/arm/dts/zynq-brcp1.dtsi
Normal file
@@ -0,0 +1,131 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 B&R Industrial Automation GmbH
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*/
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/include/ "zynq-7000.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "BRCP1 CPU";
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compatible = "br,cp1",
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"xlnx,zynq-7000";
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aliases {
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i2c0 = &i2c0;
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serial0 = &uart0;
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spi0 = &qspi;
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mmc0 = &sdhci0;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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brd_rst: board_reset {
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compatible = "br,board-reset";
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pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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leds {
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compatible = "gpio-leds";
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se_green {
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label = "S_E_GREEN";
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gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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se_red {
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label = "S_E_RED";
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gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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rdy_f_yellow {
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label = "RDY_F_YELLOW";
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gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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re_green {
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label = "R_E_GREEN";
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gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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re_red {
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label = "R_E_RED";
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gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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plk_se_green {
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label = "PLK_S_E_GREEN";
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gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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eth_se_green {
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label = "ETH_S_E_GREEN";
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gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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ledgpio: max7320@5d { /* board LED */
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status = "okay";
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compatible = "maxim,max7320";
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reg = <0x5d>;
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#gpio-cells = <2>;
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gpio-controller;
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ngpios = <8>;
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};
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pmic0: da9062@58 {
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compatible = "dlg,da9062";
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reg = <0x58>;
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};
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};
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&sdhci0 {
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status = "okay";
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max-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&qspi {
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status = "okay";
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spi-max-frequency = <100000000>;
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spi_flash: spiflash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
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spi-max-frequency = <100000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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};
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&gpio0 {
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status = "okay";
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};
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34
arch/arm/dts/zynq-brcp150-u-boot.dtsi
Normal file
34
arch/arm/dts/zynq-brcp150-u-boot.dtsi
Normal file
@@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 B&R Industrial Automation GmbH
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*/
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#include "zynq-binman-brcp1.dtsi"
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&i2c0 {
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bootph-all;
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};
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&uart0 {
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bootph-all;
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};
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&qspi {
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bootph-all;
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};
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&spi_flash {
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bootph-all;
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};
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&gpio0 {
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bootph-all;
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};
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&brd_rst {
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bootph-all;
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};
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&rs232_en {
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bootph-all;
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};
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173
arch/arm/dts/zynq-brcp150.dts
Normal file
173
arch/arm/dts/zynq-brcp150.dts
Normal file
@@ -0,0 +1,173 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 B&R Industrial Automation GmbH
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "BRCP150 CPU";
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compatible = "br,cp150",
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"xlnx,zynq-7000";
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aliases {
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i2c0 = &i2c0;
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serial0 = &uart0;
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spi0 = &qspi;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x20000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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brd_rst: board_reset {
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compatible = "br,board-reset";
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pin = <&gpio0 27 GPIO_ACTIVE_HIGH>;
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};
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/* Put this pin active high to enable RS232 debug serial */
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rs232_en: rs232_enable {
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compatible = "br,rs232-en";
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pin = <&gpio0 52 GPIO_ACTIVE_HIGH>;
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};
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leds {
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compatible = "gpio-leds";
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re_green {
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label = "R_E_GREEN";
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gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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re_red {
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label = "R_E_RED";
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gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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rdy_f_red {
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label = "RDY_F_RED";
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gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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rdy_f_yellow {
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label = "RDY_F_YELLOW";
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gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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se_green {
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label = "S_E_GREEN";
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gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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se_red {
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label = "S_E_RED";
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gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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plk_se_green {
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label = "PLK_S_E_GREEN";
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gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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eth_se_green {
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label = "ETH_S_E_GREEN";
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gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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user1_green {
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label = "USER1_GREEN";
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gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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user1_red {
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label = "USER1_RED";
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gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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user2_green {
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label = "USER2_GREEN";
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gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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user2_red {
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label = "USER2_RED";
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gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
|
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};
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};
|
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|
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&gem0 {
|
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status = "okay";
|
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phy-mode = "mii";
|
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phy-handle = <ðernet_phy>;
|
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|
||||
ethernet_phy: emio-phy@2 {
|
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reg = <2>;
|
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max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ledgpio: max7320@5d { /* board LED */
|
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status = "okay";
|
||||
compatible = "maxim,max7320";
|
||||
reg = <0x5d>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
ngpios = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
spi_flash: spiflash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
|
||||
spi-max-frequency = <100000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy0>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Since the gem0 clock is configured EMIO this dummy entry is needed */
|
||||
&clkc {
|
||||
clocks = <&clkc 16>;
|
||||
clock-names = "gem0_emio_clk";
|
||||
};
|
||||
26
arch/arm/dts/zynq-brcp170-u-boot.dtsi
Normal file
26
arch/arm/dts/zynq-brcp170-u-boot.dtsi
Normal file
@@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
#include "zynq-binman-brcp1.dtsi"
|
||||
|
||||
&i2c0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&spi_flash {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
139
arch/arm/dts/zynq-brcp170.dts
Normal file
139
arch/arm/dts/zynq-brcp170.dts
Normal file
@@ -0,0 +1,139 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "zynq-7000.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "BRCP170 CPU";
|
||||
compatible = "br,cp170",
|
||||
"xlnx,zynq-7000";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
serial0 = &uart0;
|
||||
spi0 = &qspi;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
usb_phy0: phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
re_green {
|
||||
label = "R_E_GREEN";
|
||||
gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
re_red {
|
||||
label = "R_E_RED";
|
||||
gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
rdy_f_red {
|
||||
label = "RDY_F_RED";
|
||||
gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
rdy_f_yellow {
|
||||
label = "RDY_F_YELLOW";
|
||||
gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
se_green {
|
||||
label = "S_E_GREEN";
|
||||
gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
se_red {
|
||||
label = "S_E_RED";
|
||||
gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
plk_se_green {
|
||||
label = "PLK_S_E_GREEN";
|
||||
gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
eth_se_green {
|
||||
label = "ETH_S_E_GREEN";
|
||||
gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
max-speed = <100>;
|
||||
ti,rx-internal-delay = <7>;
|
||||
ti,tx-internal-delay = <7>;
|
||||
ti,fifo-depth = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ledgpio: max7320@58 { /* board LED */
|
||||
status = "okay";
|
||||
compatible = "maxim,max7320";
|
||||
reg = <0x58>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
spi_flash: spiflash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
|
||||
spi-max-frequency = <100000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy0>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
30
arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
Normal file
30
arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
Normal file
@@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
#include "zynq-binman-brcp1.dtsi"
|
||||
|
||||
&i2c0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&spi_flash {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&brd_rst {
|
||||
bootph-all;
|
||||
};
|
||||
28
arch/arm/dts/zynq-brcp1_1r.dts
Normal file
28
arch/arm/dts/zynq-brcp1_1r.dts
Normal file
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "zynq-brcp1.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x8000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <7>;
|
||||
ti,tx-internal-delay = <7>;
|
||||
ti,fifo-depth = <0>;
|
||||
max-speed = <1000>;
|
||||
};
|
||||
};
|
||||
1
arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
Symbolic link
1
arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
Symbolic link
@@ -0,0 +1 @@
|
||||
zynq-brcp1_1r-u-boot.dtsi
|
||||
30
arch/arm/dts/zynq-brcp1_1r_switch.dts
Normal file
30
arch/arm/dts/zynq-brcp1_1r_switch.dts
Normal file
@@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "zynq-brcp1.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x8000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "gmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <100>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
/* Since the gem0 clock is configured EMIO this dummy entry is needed */
|
||||
&clkc {
|
||||
clocks = <&clkc 16>;
|
||||
clock-names = "gem0_emio_clk";
|
||||
};
|
||||
1
arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
Symbolic link
1
arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
Symbolic link
@@ -0,0 +1 @@
|
||||
zynq-brcp1_1r-u-boot.dtsi
|
||||
21
arch/arm/dts/zynq-brcp1_2r.dts
Normal file
21
arch/arm/dts/zynq-brcp1_2r.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "zynq-brcp1.dtsi"
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy>;
|
||||
|
||||
ethernet_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <7>;
|
||||
ti,tx-internal-delay = <7>;
|
||||
ti,fifo-depth = <0>;
|
||||
max-speed = <1000>;
|
||||
};
|
||||
};
|
||||
30
arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
Normal file
30
arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
Normal file
@@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
#include "zynq-binman-brcp1.dtsi"
|
||||
|
||||
&i2c0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&spi_flash {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&brd_rst {
|
||||
bootph-all;
|
||||
};
|
||||
157
arch/arm/dts/zynq-brsmarc2.dts
Normal file
157
arch/arm/dts/zynq-brsmarc2.dts
Normal file
@@ -0,0 +1,157 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2024 B&R Industrial Automation GmbH
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "zynq-7000.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "BRSMARC2 CPU";
|
||||
compatible = "br,smarc2",
|
||||
"xlnx,zynq-7000";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
serial0 = &uart0;
|
||||
spi0 = &qspi;
|
||||
mmc0 = &sdhci0;
|
||||
can0 = &can0;
|
||||
can1 = &can1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
usb_phy0: phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
brd_rst: board_reset {
|
||||
compatible = "br,board-reset";
|
||||
pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
plk_se_green {
|
||||
label = "PLK_S_E_GREEN";
|
||||
gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
plk_se_red {
|
||||
label = "PLK_S_E_RED";
|
||||
gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
rdy_f_yellow {
|
||||
label = "RDY_F_YELLOW";
|
||||
gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
re_green {
|
||||
label = "R_E_GREEN";
|
||||
gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
re_red {
|
||||
label = "R_E_RED";
|
||||
gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy0>;
|
||||
|
||||
ethernet_phy0: ethernet-phy@1 {
|
||||
ti,ledcr = <0x0480>;
|
||||
ti,rgmii-rxclk-shift;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðernet_phy1>;
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
|
||||
ethernet_phy1: ethernet-phy@3{
|
||||
ti,ledcr = <0x0480>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
resetc: rststm@60 { /* reset controller */
|
||||
compatible = "bur,rststm";
|
||||
reg = <0x60>;
|
||||
hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
|
||||
cooling-min-state = <0>;
|
||||
cooling-max-state = <1>; /* reset gets fired */
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
ledgpio: max7320@5d { /* board LED */
|
||||
status = "okay";
|
||||
compatible = "maxim,max7320";
|
||||
reg = <0x5d>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
max-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
spi_flash: spiflash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
|
||||
spi-max-frequency = <100000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
usb-phy = <&usb_phy0>;
|
||||
};
|
||||
@@ -58,5 +58,6 @@ config ZYNQ_SDHCI_MAX_FREQ
|
||||
|
||||
source "board/xilinx/Kconfig"
|
||||
source "board/xilinx/zynq/Kconfig"
|
||||
source "board/BuR/zynq/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
14
board/BuR/zynq/Kconfig
Normal file
14
board/BuR/zynq/Kconfig
Normal file
@@ -0,0 +1,14 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
if ARCH_ZYNQ
|
||||
|
||||
config TARGET_ZYNQ_BR
|
||||
bool "Support BR Zynq builds"
|
||||
depends on SYS_VENDOR = "BuR"
|
||||
select BINMAN
|
||||
select SPL_BINMAN_FDT
|
||||
|
||||
endif
|
||||
|
||||
source "board/BuR/common/Kconfig"
|
||||
11
board/BuR/zynq/MAINTAINERS
Normal file
11
board/BuR/zynq/MAINTAINERS
Normal file
@@ -0,0 +1,11 @@
|
||||
ZYNQ BOARD
|
||||
M: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
|
||||
S: Maintained
|
||||
F: board/BuR/zynq/
|
||||
F: board/BuR/common/
|
||||
F: include/configs/brzynq.h
|
||||
F: arch/arm/dts/zynq-br*
|
||||
F: configs/brcp1_*
|
||||
F: configs/brcp150_defconfig
|
||||
F: configs/brcp170_defconfig
|
||||
F: configs/brsmarc2_defconfig
|
||||
15
board/BuR/zynq/Makefile
Normal file
15
board/BuR/zynq/Makefile
Normal file
@@ -0,0 +1,15 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
|
||||
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
|
||||
|
||||
obj-y := ../common/common.o
|
||||
obj-y += ../common/br_resetc.o
|
||||
obj-y += common/board.o
|
||||
obj-y += $(hw-platform-y)/board.o
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
|
||||
|
||||
# Suppress "warning: function declaration isn't a prototype"
|
||||
CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
|
||||
4
board/BuR/zynq/brcp150/board.c
Normal file
4
board/BuR/zynq/brcp150/board.c
Normal file
@@ -0,0 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
278
board/BuR/zynq/brcp150/ps7_init_gpl.c
Normal file
278
board/BuR/zynq/brcp150/ps7_init_gpl.c
Normal file
@@ -0,0 +1,278 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000801U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001001U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001003U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000802U),
|
||||
EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01403U),
|
||||
EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000801U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400800U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FF844DU),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x000003E0U),
|
||||
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x000003E1U),
|
||||
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
|
||||
EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
|
||||
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
|
||||
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
|
||||
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
|
||||
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
|
||||
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
4
board/BuR/zynq/brcp170/board.c
Normal file
4
board/BuR/zynq/brcp170/board.c
Normal file
@@ -0,0 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
274
board/BuR/zynq/brcp170/ps7_init_gpl.c
Normal file
274
board/BuR/zynq/brcp170/ps7_init_gpl.c
Normal file
@@ -0,0 +1,274 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
|
||||
EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
|
||||
EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DF844DU),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
|
||||
EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U),
|
||||
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U),
|
||||
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
|
||||
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U),
|
||||
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U),
|
||||
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
4
board/BuR/zynq/brcp1_1r/board.c
Normal file
4
board/BuR/zynq/brcp1_1r/board.c
Normal file
@@ -0,0 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
274
board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
Normal file
274
board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
Normal file
@@ -0,0 +1,274 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0003C000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000300U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x000FA240U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0003C000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00101001U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001401U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000A02U),
|
||||
EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01901U),
|
||||
EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00500800U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
|
||||
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
|
||||
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
|
||||
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
4
board/BuR/zynq/brcp1_1r_switch/board.c
Normal file
4
board/BuR/zynq/brcp1_1r_switch/board.c
Normal file
@@ -0,0 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
270
board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
Normal file
270
board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
Normal file
@@ -0,0 +1,270 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U),
|
||||
EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
|
||||
EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
|
||||
EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD84CDU),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
|
||||
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
|
||||
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
|
||||
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U),
|
||||
EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
4
board/BuR/zynq/brcp1_2r/board.c
Normal file
4
board/BuR/zynq/brcp1_2r/board.c
Normal file
@@ -0,0 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
277
board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
Normal file
277
board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
Normal file
@@ -0,0 +1,277 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA3C0U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0002E000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U),
|
||||
EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U),
|
||||
EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00101400U),
|
||||
EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
|
||||
EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
|
||||
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U),
|
||||
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U),
|
||||
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U),
|
||||
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U),
|
||||
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U),
|
||||
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
30
board/BuR/zynq/brsmarc2/board.c
Normal file
30
board/BuR/zynq/brsmarc2/board.c
Normal file
@@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <i2c.h>
|
||||
#include <init.h>
|
||||
#include "../../common/br_resetc.h"
|
||||
#include "../../common/bur_common.h"
|
||||
|
||||
int board_boot_key(void)
|
||||
{
|
||||
unsigned char u8buf = 0;
|
||||
int rc;
|
||||
|
||||
rc = br_resetc_regget(RSTCTRL_ENHSTATUS, &u8buf);
|
||||
if (rc == 0)
|
||||
return (u8buf & 0x1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
int br_board_late_init(void)
|
||||
{
|
||||
brdefaultip_setup(0, 0x57);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
276
board/BuR/zynq/brsmarc2/ps7_init_gpl.c
Normal file
276
board/BuR/zynq/brsmarc2/ps7_init_gpl.c
Normal file
@@ -0,0 +1,276 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <asm/arch/ps7_init_gpl.h>
|
||||
|
||||
unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U),
|
||||
EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U),
|
||||
EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
|
||||
EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF6666U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
|
||||
EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
|
||||
EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
|
||||
EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
|
||||
EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U),
|
||||
EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
|
||||
EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
|
||||
EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
|
||||
EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
|
||||
EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
|
||||
EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
|
||||
EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U),
|
||||
EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U),
|
||||
EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
|
||||
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U),
|
||||
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U),
|
||||
EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
|
||||
EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
|
||||
EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_WRITE(0XF8000004, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
231
board/BuR/zynq/common/board.c
Normal file
231
board/BuR/zynq/common/board.c
Normal file
@@ -0,0 +1,231 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Board functions for B&R brcp150, brcp170, brcp1, brsmarc2 Board
|
||||
*
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com
|
||||
*
|
||||
*/
|
||||
|
||||
#include <fdtdec.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <init.h>
|
||||
#include <i2c.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <command.h>
|
||||
#include <binman.h>
|
||||
#include "../../common/br_resetc.h"
|
||||
#include "../../common/bur_common.h"
|
||||
|
||||
#include <fdt_support.h>
|
||||
#include <spi_flash.h>
|
||||
#include <fpga.h>
|
||||
#include <zynqpl.h>
|
||||
|
||||
#define RSTCTRL_CTRLSPEC_nPCIRST 0x1
|
||||
|
||||
__weak int br_board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(FPGA)
|
||||
const char *fpga_paths[2] = { "/binman/blob-ext@4",
|
||||
"/binman/blob-ext@1"};
|
||||
|
||||
static int start_fpga(unsigned int bank)
|
||||
{
|
||||
struct spi_flash *flash_dev;
|
||||
ofnode fpga_node;
|
||||
void *buf;
|
||||
|
||||
u32 flash_offset, flash_size;
|
||||
int rc;
|
||||
|
||||
fpga_node = ofnode_path(fpga_paths[bank]);
|
||||
|
||||
if (!ofnode_valid(fpga_node)) {
|
||||
printf("WARN: binman node not found %s\n", fpga_paths[bank]);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
flash_offset = ofnode_read_u32_default(fpga_node, "offset", ~0UL);
|
||||
flash_size = ofnode_read_u32_default(fpga_node, "size", ~0UL);
|
||||
|
||||
if (flash_offset == ~0UL || flash_size == ~0UL) {
|
||||
printf("WARN: invalid fpga 'offset, size' in fdt (0x%x, 0x%x)",
|
||||
flash_offset, flash_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
printf("loading bitstream from bank #%d (0x%08x / 0x%08x)\n", bank,
|
||||
flash_offset, flash_size);
|
||||
|
||||
flash_dev = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
|
||||
CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
|
||||
|
||||
if (rc) {
|
||||
printf("WARN: cannot probe SPI-flash for bitstream!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
buf = kmalloc(flash_size, 0);
|
||||
if (!buf) {
|
||||
spi_flash_free(flash_dev);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
debug("using buf @ %p, flashbase: 0x%08x, len: 0x%08x\n",
|
||||
buf, flash_offset, flash_size);
|
||||
|
||||
rc = spi_flash_read(flash_dev, flash_offset, flash_size, buf);
|
||||
|
||||
spi_flash_free(flash_dev);
|
||||
|
||||
if (rc) {
|
||||
printf("WARN: cannot read bitstream from spi-flash!\n");
|
||||
kfree(buf);
|
||||
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
rc = fpga_loadbitstream(0, buf, flash_size, BIT_FULL);
|
||||
if (rc) {
|
||||
printf("WARN: FPGA configuration from bank #%d failed!\n", bank);
|
||||
kfree(buf);
|
||||
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
kfree(buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
const char *boot_gpios[] = { "br,rs232-en",
|
||||
"br,board-reset",
|
||||
NULL};
|
||||
|
||||
/* spl stage */
|
||||
int board_init(void)
|
||||
{
|
||||
struct gpio_desc gpio;
|
||||
int node;
|
||||
int rc;
|
||||
|
||||
/* peripheral RESET on PSOC reset-controller */
|
||||
rc = br_resetc_regset(RSTCTRL_SPECGPIO_O, RSTCTRL_CTRLSPEC_nPCIRST);
|
||||
if (rc != 0)
|
||||
printf("ERROR: cannot write to resetc (nPCIRST)!\n");
|
||||
|
||||
for (int i = 0; boot_gpios[i]; i++) {
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, boot_gpios[i]);
|
||||
|
||||
if (node < 0) {
|
||||
printf("INFO: %s not found!\n", boot_gpios[i]);
|
||||
} else {
|
||||
rc = gpio_request_by_name_nodev(offset_to_ofnode(node), "pin",
|
||||
0, &gpio, GPIOD_IS_OUT);
|
||||
|
||||
if (!rc)
|
||||
dm_gpio_set_value(&gpio, 1);
|
||||
else
|
||||
printf("ERROR: failed to setup %s!\n", boot_gpios[i]);
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(FPGA)
|
||||
unsigned int bmode;
|
||||
unsigned int bank;
|
||||
|
||||
rc = br_resetc_bmode_get(&bmode);
|
||||
if (rc) {
|
||||
printf("WARN: can't get Boot Mode!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* use golden FPGA image in case of special boot flow (PME, BootAR, USB, Net ...) */
|
||||
bank = ((bmode == 0) || (bmode == 12)) ? 1 : 0;
|
||||
|
||||
/* bring up FPGA */
|
||||
if (start_fpga(bank) != 0) {
|
||||
printf("WARN: cannot start fpga from bank %d, trying bank %d!\n", bank, bank ^ 1);
|
||||
bank ^= 1;
|
||||
start_fpga(bank);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* PMIC buckboost regulator workaround:
|
||||
* The DA9062 PMIC can switch its buckboost regulator output
|
||||
* between PFM and PWM mode for eco-purpose.
|
||||
* In very rare situations this transition leads into a non-
|
||||
* functional buckboost regulator with zero output.
|
||||
* With this workaround we prevent this with turning this
|
||||
* feature off by forcing PWM-mode if auto-mode is selected.
|
||||
*/
|
||||
static void pmic_fixup(int addr)
|
||||
{
|
||||
u8 regs[] = { 0x9E, 0x9D, 0xA0, 0x9F };
|
||||
struct udevice *i2cdev = NULL;
|
||||
unsigned int i;
|
||||
u8 val;
|
||||
int rc;
|
||||
|
||||
i2c_get_chip_for_busnum(0, addr, 1, &i2cdev);
|
||||
if (!i2cdev)
|
||||
return;
|
||||
|
||||
printf("PMIC: fixup buckboost at i2c device 0x%x\n", addr);
|
||||
|
||||
for (i = 0; i < sizeof(regs); i++) {
|
||||
rc = dm_i2c_read(i2cdev, regs[i], &val, 1);
|
||||
if (rc == 0 && val == 0xC0) {
|
||||
val = 0x80;
|
||||
dm_i2c_write(i2cdev, regs[i], &val, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
ofnode node;
|
||||
u32 addr;
|
||||
|
||||
br_resetc_bmode();
|
||||
br_board_late_init();
|
||||
|
||||
node = ofnode_by_compatible(ofnode_null(), "dlg,da9062");
|
||||
|
||||
if (!ofnode_valid(node))
|
||||
return 0;
|
||||
|
||||
if (!ofnode_read_u32(node, "reg", &addr))
|
||||
pmic_fixup(addr);
|
||||
else
|
||||
printf("WARN: cannot read PMIC address!");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
if (fdtdec_setup_mem_size_base() != 0)
|
||||
return -EINVAL;
|
||||
|
||||
zynq_ddrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
109
board/BuR/zynq/env/brcp1.env
vendored
Normal file
109
board/BuR/zynq/env/brcp1.env
vendored
Normal file
@@ -0,0 +1,109 @@
|
||||
autoload=0
|
||||
b_break=0
|
||||
fpgastatus=disabled
|
||||
/* Memory variable */
|
||||
scradr=0xC0000
|
||||
fdtbackaddr=0x4000000
|
||||
loadaddr=CONFIG_SYS_LOAD_ADDR
|
||||
|
||||
/* PREBOOT */
|
||||
preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
|
||||
|
||||
/* SPI layout variables */
|
||||
cfg_addr=
|
||||
fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
|
||||
fdt get value cfgsize_spi /binman/blob-ext@0 size
|
||||
|
||||
fpga_addr=
|
||||
fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
|
||||
fdt get value fpgasize_spi /binman/blob-ext@1 size
|
||||
|
||||
os_addr=
|
||||
fdt get value osaddr_spi /binman/blob-ext@2 offset &&
|
||||
fdt get value ossize_spi /binman/blob-ext@2 size
|
||||
|
||||
dtb_addr=
|
||||
fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
|
||||
fdt get value dtbsize_spi /binman/blob-ext@3 size
|
||||
|
||||
setupaddr_spi=
|
||||
fdt addr ${fdtcontroladdr};
|
||||
run dtb_addr; run os_addr;
|
||||
run fpga_addr; run cfg_addr
|
||||
|
||||
/* IP setup */
|
||||
brdefaultip=
|
||||
if test -r ${ipaddr}; then;
|
||||
else
|
||||
setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
|
||||
setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
|
||||
fi
|
||||
|
||||
/* Boot orders */
|
||||
b_tgts_std=mmc0 mmc1 spi usb0 usb1 net
|
||||
b_tgts_rcy=spi usb0 usb1 net
|
||||
b_tgts_pme=net usb0 usb1 mmc spi
|
||||
|
||||
/* Boot targets */
|
||||
b_mmc0=
|
||||
run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
|
||||
run vxargs && bootm ${loadaddr}
|
||||
|
||||
b_mmc1=
|
||||
run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg &&
|
||||
run vxargs &&
|
||||
sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
|
||||
fdt addr ${fdtbackaddr} &&
|
||||
bootm ${loadaddr} - ${fdtbackaddr}
|
||||
|
||||
b_spi=
|
||||
run fpga; sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
|
||||
run vxargs && bootm ${loadaddr}
|
||||
|
||||
b_net=run fpga; tftp ${scradr} netscript.img && source ${scradr}
|
||||
b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
|
||||
b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
|
||||
|
||||
/* FPGA setup */
|
||||
fpga=
|
||||
setenv fpgastatus disabled;
|
||||
sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
|
||||
fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
|
||||
setenv fpgastatus okay
|
||||
|
||||
/* Configuration preboot*/
|
||||
cfgscr=
|
||||
sf probe &&
|
||||
sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
|
||||
source ${scradr}
|
||||
|
||||
/* OS Boot */
|
||||
fdt_fixup=
|
||||
run cfgscr; run vxfdt
|
||||
|
||||
vxargs=
|
||||
setenv bootargs gem(0,0)host:vxWorks h=${serverip}
|
||||
e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
|
||||
|
||||
vxfdt=
|
||||
fdt set /fpga/pci status ${fpgastatus};
|
||||
fdt set /fpga status ${fpgastatus}
|
||||
|
||||
/* Boot code */
|
||||
b_default=
|
||||
run b_deftgts;
|
||||
for target in ${b_tgts}; do
|
||||
run b_${target};
|
||||
if test ${b_break} = 1; then;
|
||||
exit;
|
||||
fi;
|
||||
done
|
||||
|
||||
b_deftgts=
|
||||
if test ${b_mode} = 12; then
|
||||
setenv b_tgts ${b_tgts_pme};
|
||||
elif test ${b_mode} = 0; then
|
||||
setenv b_tgts ${b_tgts_rcy};
|
||||
else
|
||||
setenv b_tgts ${b_tgts_std};
|
||||
fi
|
||||
119
board/BuR/zynq/env/brcp150.env
vendored
Normal file
119
board/BuR/zynq/env/brcp150.env
vendored
Normal file
@@ -0,0 +1,119 @@
|
||||
autoload=0
|
||||
b_break=0
|
||||
fpgastatus=disabled
|
||||
/* Memory variable */
|
||||
scradr=0xC0000
|
||||
fdtbackaddr=0x4000000
|
||||
loadaddr=CONFIG_SYS_LOAD_ADDR
|
||||
|
||||
/* PREBOOT */
|
||||
preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1
|
||||
|
||||
/* SPI layout variables */
|
||||
cfg_addr=
|
||||
fdt get value cfgaddr_spi /binman/blob-ext@0 offset &&
|
||||
fdt get value cfgsize_spi /binman/blob-ext@0 size
|
||||
|
||||
fpga_addr=
|
||||
fdt get value fpgaaddr_spi /binman/blob-ext@1 offset &&
|
||||
fdt get value fpgasize_spi /binman/blob-ext@1 size
|
||||
|
||||
os_addr=
|
||||
fdt get value osaddr_spi /binman/blob-ext@2 offset &&
|
||||
fdt get value ossize_spi /binman/blob-ext@2 size
|
||||
|
||||
dtb_addr=
|
||||
fdt get value dtbaddr_spi /binman/blob-ext@3 offset &&
|
||||
fdt get value dtbsize_spi /binman/blob-ext@3 size
|
||||
|
||||
opt_addr=
|
||||
fdt get value optaddr_spi /binman/blob-ext@5 offset &&
|
||||
fdt get value optsize_spi /binman/blob-ext@5 size
|
||||
|
||||
setupaddr_spi=
|
||||
fdt addr ${fdtcontroladdr};
|
||||
run dtb_addr; run os_addr;
|
||||
run fpga_addr; run cfg_addr;
|
||||
run opt_addr
|
||||
|
||||
/* IP setup */
|
||||
brdefaultip=
|
||||
if test -r ${ipaddr}; then;
|
||||
else
|
||||
setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;
|
||||
setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0;
|
||||
fi
|
||||
|
||||
/* Boot orders */
|
||||
b_tgts_std=mmc0 mmc1 fpga spi usb0 usb1 net
|
||||
b_tgts_rcy=spi usb0 usb1 net
|
||||
b_tgts_pme=net usb0 usb1 mmc spi
|
||||
|
||||
/* Boot targets */
|
||||
b_mmc0=
|
||||
mmc dev 0; load mmc 0 ${loadaddr} arimg.itb &&
|
||||
run vxargs && bootm ${loadaddr}
|
||||
|
||||
b_mmc1=
|
||||
mmc dev 0; load mmc 0 ${loadaddr} arimg &&
|
||||
run vxargs &&
|
||||
sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} &&
|
||||
fdt addr ${fdtbackaddr} &&
|
||||
bootm ${loadaddr} - ${fdtbackaddr}
|
||||
|
||||
b_spi=
|
||||
sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} &&
|
||||
run vxargs && bootm ${loadaddr}
|
||||
|
||||
b_net=tftp ${scradr} netscript.img && source ${scradr}
|
||||
b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}
|
||||
b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}
|
||||
|
||||
/* FPGA setup */
|
||||
b_fpga=
|
||||
setenv fpgastatus disabled;
|
||||
sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} &&
|
||||
fpga loadb 0 ${loadaddr} ${fpgasize_spi} &&
|
||||
setenv fpgastatus okay
|
||||
|
||||
/* Configuration preboot*/
|
||||
cfgscr=
|
||||
sf probe &&
|
||||
sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} &&
|
||||
source ${scradr}
|
||||
|
||||
cfgoptsct=
|
||||
sf probe &&
|
||||
sf read ${scradr} ${optaddr_spi} ${optsize_spi} &&
|
||||
source ${scradr}
|
||||
|
||||
/* OS Boot */
|
||||
fdt_fixup=
|
||||
run cfgscr; run cfgoptsct; run vxfdt
|
||||
|
||||
vxargs=
|
||||
setenv bootargs gem(0,0)host:vxWorks h=${serverip}
|
||||
e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1
|
||||
|
||||
vxfdt=
|
||||
fdt set /fpga/pci status ${fpgastatus};
|
||||
fdt set /fpga status ${fpgastatus}
|
||||
|
||||
/* Boot code */
|
||||
b_default=
|
||||
run b_deftgts;
|
||||
for target in ${b_tgts}; do
|
||||
run b_${target};
|
||||
if test ${b_break} = 1; then;
|
||||
exit;
|
||||
fi;
|
||||
done
|
||||
|
||||
b_deftgts=
|
||||
if test ${b_mode} = 12; then
|
||||
setenv b_tgts ${b_tgts_pme};
|
||||
elif test ${b_mode} = 0; then
|
||||
setenv b_tgts ${b_tgts_rcy};
|
||||
else
|
||||
setenv b_tgts ${b_tgts_std};
|
||||
fi
|
||||
121
configs/brcp150_defconfig
Normal file
121
configs/brcp150_defconfig
Normal file
@@ -0,0 +1,121 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="BuR"
|
||||
CONFIG_SYS_CONFIG_NAME="brzynq"
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SOURCE_FILE="env/brcp150"
|
||||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp150"
|
||||
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xFFFFFE00
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x2000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x30000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
|
||||
CONFIG_TARGET_ZYNQ_BR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
|
||||
CONFIG_SPL_LOAD_FIT_FULL=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_OF_ENV_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_CLOCKS=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
|
||||
CONFIG_SPL_CPU=y
|
||||
CONFIG_SPL_FPGA=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_HUSH_MODERN_PARSER=y
|
||||
CONFIG_SYS_PROMPT="-> "
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_BOOTP_MAY_FAIL=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQPL=y
|
||||
CONFIG_MAX7320_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_HISPD_BROKEN=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SILICONKAISER=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_S28HX_T=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_ZBIT=y
|
||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||
CONFIG_PHY_TI_GENERIC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_TIMER_COUNTS_DOWN=y
|
||||
# CONFIG_SHA256 is not set
|
||||
CONFIG_SPL_CRC32=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
120
configs/brcp170_defconfig
Normal file
120
configs/brcp170_defconfig
Normal file
@@ -0,0 +1,120 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="BuR"
|
||||
CONFIG_SYS_CONFIG_NAME="brzynq"
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SOURCE_FILE="env/brcp1"
|
||||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp170"
|
||||
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xFFFFFE00
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x2000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x30000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
|
||||
CONFIG_TARGET_ZYNQ_BR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
|
||||
CONFIG_SPL_LOAD_FIT_FULL=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_OF_ENV_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_CLOCKS=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
|
||||
CONFIG_SPL_CPU=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_HUSH_MODERN_PARSER=y
|
||||
CONFIG_SYS_PROMPT="-> "
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_BOOTP_MAY_FAIL=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQPL=y
|
||||
CONFIG_MAX7320_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_HISPD_BROKEN=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SILICONKAISER=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_S28HX_T=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_ZBIT=y
|
||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||
CONFIG_PHY_TI_GENERIC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_TIMER_COUNTS_DOWN=y
|
||||
# CONFIG_SHA256 is not set
|
||||
CONFIG_SPL_CRC32=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
120
configs/brcp1_1r_defconfig
Normal file
120
configs/brcp1_1r_defconfig
Normal file
@@ -0,0 +1,120 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="BuR"
|
||||
CONFIG_SYS_CONFIG_NAME="brzynq"
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SOURCE_FILE="env/brcp1"
|
||||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r"
|
||||
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xFFFFFE00
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x2000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x30000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
|
||||
CONFIG_TARGET_ZYNQ_BR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
|
||||
CONFIG_SPL_LOAD_FIT_FULL=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_OF_ENV_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_CLOCKS=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
|
||||
CONFIG_SPL_CPU=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_HUSH_MODERN_PARSER=y
|
||||
CONFIG_SYS_PROMPT="-> "
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_BOOTP_MAY_FAIL=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQPL=y
|
||||
CONFIG_MAX7320_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_HISPD_BROKEN=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SILICONKAISER=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_S28HX_T=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_ZBIT=y
|
||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_TIMER_COUNTS_DOWN=y
|
||||
# CONFIG_SHA256 is not set
|
||||
CONFIG_SPL_CRC32=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
121
configs/brcp1_1r_switch_defconfig
Normal file
121
configs/brcp1_1r_switch_defconfig
Normal file
@@ -0,0 +1,121 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="BuR"
|
||||
CONFIG_SYS_CONFIG_NAME="brzynq"
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SOURCE_FILE="env/brcp1"
|
||||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r_switch"
|
||||
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xFFFFFE00
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x2000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x30000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
|
||||
CONFIG_TARGET_ZYNQ_BR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
|
||||
CONFIG_SPL_LOAD_FIT_FULL=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_OF_ENV_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_CLOCKS=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
|
||||
CONFIG_SPL_CPU=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_HUSH_MODERN_PARSER=y
|
||||
CONFIG_SYS_PROMPT="-> "
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_BOOTP_MAY_FAIL=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQPL=y
|
||||
CONFIG_MAX7320_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_HISPD_BROKEN=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SILICONKAISER=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_S28HX_T=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_ZBIT=y
|
||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_TIMER_COUNTS_DOWN=y
|
||||
# CONFIG_SHA256 is not set
|
||||
CONFIG_SPL_CRC32=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
120
configs/brcp1_2r_defconfig
Normal file
120
configs/brcp1_2r_defconfig
Normal file
@@ -0,0 +1,120 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="BuR"
|
||||
CONFIG_SYS_CONFIG_NAME="brzynq"
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SOURCE_FILE="env/brcp1"
|
||||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_2r"
|
||||
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xFFFFFE00
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x2000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x30000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
|
||||
CONFIG_TARGET_ZYNQ_BR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
|
||||
CONFIG_SPL_LOAD_FIT_FULL=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_OF_ENV_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_CLOCKS=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
|
||||
CONFIG_SPL_CPU=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_HUSH_MODERN_PARSER=y
|
||||
CONFIG_SYS_PROMPT="-> "
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_BOOTP_MAY_FAIL=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQPL=y
|
||||
CONFIG_MAX7320_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_HISPD_BROKEN=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SILICONKAISER=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_S28HX_T=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_ZBIT=y
|
||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_TIMER_COUNTS_DOWN=y
|
||||
# CONFIG_SHA256 is not set
|
||||
CONFIG_SPL_CRC32=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
120
configs/brsmarc2_defconfig
Normal file
120
configs/brsmarc2_defconfig
Normal file
@@ -0,0 +1,120 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="BuR"
|
||||
CONFIG_SYS_CONFIG_NAME="brzynq"
|
||||
CONFIG_SYS_L2CACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x4000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SOURCE_FILE="env/brcp1"
|
||||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x3
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2"
|
||||
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000
|
||||
# CONFIG_SPL_MMC is not set
|
||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||
CONFIG_SPL_STACK=0xFFFFFE00
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x20000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x2000000
|
||||
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x30000
|
||||
# CONFIG_SPL_FS_FAT is not set
|
||||
# CONFIG_SPL_LIBDISK_SUPPORT is not set
|
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
|
||||
CONFIG_TARGET_ZYNQ_BR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000
|
||||
CONFIG_SPL_LOAD_FIT_FULL=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_OF_ENV_SETUP=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run b_default"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_CLOCKS=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_PAD_TO=0x0
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
|
||||
CONFIG_SPL_CPU=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_HUSH_MODERN_PARSER=y
|
||||
CONFIG_SYS_PROMPT="-> "
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_BOOTP_MAY_FAIL=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQPL=y
|
||||
CONFIG_MAX7320_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_HISPD_BROKEN=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SILICONKAISER=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_S28HX_T=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MT35XU=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_ZBIT=y
|
||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_TIMER_COUNTS_DOWN=y
|
||||
# CONFIG_SHA256 is not set
|
||||
CONFIG_SPL_CRC32=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
21
include/configs/brzynq.h
Normal file
21
include/configs/brzynq.h
Normal file
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Config file for BR Zynq board
|
||||
*
|
||||
* Copyright (C) 2024
|
||||
* B&R Industrial Automation GmbH - http://www.br-automation.com/
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_BRZYNQ_H__
|
||||
#define __CONFIG_BRZYNQ_H__
|
||||
|
||||
/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */
|
||||
#if IS_ENABLED(CONFIG_SPL_FPGA)
|
||||
#define PHY_ANEG_TIMEOUT 8000
|
||||
#endif
|
||||
|
||||
/* Use top mapped SRAM */
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x2000
|
||||
|
||||
#endif /* __CONFIG_BRZYNQ_H__ */
|
||||
Reference in New Issue
Block a user