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net: fec_mxc: Fix clk_ref rate on iMX93

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i.MX93 FEC ENET port supports two mode: RGMII and RMII. For RGMII,
there is an internal /2 divider, so the freq needs to set with (*2),
otherwise the speed will not reach 1G and cause communication error
in some network environments. For RMII, the clk path is
ccm -> enet tx_clk pin -> pad loop back to enet, no /2 divider.

So fix for RGMII mode with freq multiplied by 2.

Fixes: 09de565f76 ("net: fec_mxc: support i.MX93")
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
2024-09-24 15:31:59 +08:00
committed by Fabio Estevam
parent be847fafa7
commit 94d02f13db
1 changed files with 5 additions and 2 deletions
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7
drivers/net/fec_mxc.c
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@@ -1210,10 +1210,13 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
else if (interface == PHY_INTERFACE_MODE_RGMII ||
interface == PHY_INTERFACE_MODE_RGMII_ID ||
interface == PHY_INTERFACE_MODE_RGMII_RXID ||
interface == PHY_INTERFACE_MODE_RGMII_TXID)
interface == PHY_INTERFACE_MODE_RGMII_TXID) {
freq = 125000000;
else
if (is_imx93())
freq = freq << 1;
} else {
return -EINVAL;
}
ret = clk_set_rate(clk_ref, freq);
if (ret < 0)