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pci: zynqmp: Fix the pcireg base

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The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/20250516092314.939424-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Venkatesh Yadav Abbarapu
2025-05-16 14:53:14 +05:30
committed by Michal Simek
parent b22a276f03
commit 967eebcd85
1 changed files with 7 additions and 0 deletions
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7
drivers/pci/pcie-xilinx-nwl.c
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@@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
return PTR_ERR(pcie->breg_base);
pcie->phys_breg_base = res.start;
ret = dev_read_resource_byname(dev, "pcireg", &res);
if (ret)
return ret;
pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(pcie->pcireg_base))
return PTR_ERR(pcie->pcireg_base);
ret = dev_read_resource_byname(dev, "cfg", &res);
if (ret)
return ret;