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Merge tag 'u-boot-rockchip-20250508' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/26117

- New Board support: rk3566 LCKFB TaishanPi, rk3588 Xunlong Orange Pi 5
  Max;
- Add rk3288 rmii support;
- pinctrl driver fix;
- binman description update;
This commit is contained in:
Tom Rini
2025-05-08 08:29:17 -06:00
parent 48db49b097 115a0cb9a2
commit ac204f07b2
68 changed files with 469 additions and 281 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/dts/rk3288-u-boot.dtsi
View File

@@ -46,30 +46,6 @@
};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
rom {
filename = "u-boot.rom";
size = <0x400000>;
pad-byte = <0xff>;
mkimage {
args = "-n rk3288 -T rkspi";
u-boot-spl {
};
};
u-boot-img {
offset = <0x20000>;
};
u-boot {
offset = <0x300000>;
};
fdtmap {
};
};
};
#endif
&bus_intmem {
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk3288-ddr-sram";

8
arch/arm/dts/rk3288-veyron-u-boot.dtsi
View File

@@ -11,6 +11,14 @@
};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE)
&binman {
simple-bin-spi {
size = <0x400000>;
};
};
#endif
&dmc {
logic-supply = <&vdd_logic>;
rockchip,odt-disable-freq = <333000000>;

4
arch/arm/dts/rk3399-gru-u-boot.dtsi
View File

@@ -15,11 +15,13 @@
};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE)
&binman {
rom {
simple-bin-spi {
size = <0x800000>;
};
};
#endif
&cros_ec {
ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;

35
arch/arm/dts/rk3399-u-boot.dtsi
View File

@@ -29,41 +29,6 @@
};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
multiple-images;
rom {
filename = "u-boot.rom";
size = <0x400000>;
pad-byte = <0xff>;
mkimage {
args = "-n rk3399 -T rkspi";
multiple-data-files;
#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
rockchip-tpl {
};
#elif defined(CONFIG_TPL)
u-boot-tpl {
};
#endif
u-boot-spl {
};
};
fit {
type = "blob";
filename = "u-boot.itb";
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
};
u-boot {
offset = <0x300000>;
};
fdtmap {
};
};
};
#endif /* CONFIG_ROCKCHIP_SPI_IMAGE && CONFIG_HAS_ROM */
&cru {
bootph-all;
};

11
arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
&rgb_led_r {
default-state = "off";
};
&rgb_led_b {
default-state = "off";
};

20
arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi Normal file
View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588-u-boot.dtsi"
&fspim2_pins {
bootph-pre-ram;
bootph-some-ram;
};
&sdhci {
cap-mmc-highspeed;
mmc-hs200-1_8v;
};
&sfc {
flash@0 {
bootph-pre-ram;
bootph-some-ram;
};
};

291
arch/arm/dts/rockchip-u-boot.dtsi
View File

@@ -5,6 +5,36 @@
#include <config.h>
#ifdef CONFIG_ARM64
#define FIT_ARCH "arm64"
#else
#define FIT_ARCH "arm"
#endif
#if defined(CONFIG_SPL_GZIP)
#define FIT_UBOOT_COMP "gzip"
#elif defined(CONFIG_SPL_LZMA)
#define FIT_UBOOT_COMP "lzma"
#else
#define FIT_UBOOT_COMP "none"
#endif
/*
* SHA256 should be enabled in SPL when signature validation is involved,
* CRC32 should only be used for basic checksum validation of FIT images.
*/
#if defined(CONFIG_SPL_FIT_SIGNATURE)
#if defined(CONFIG_SPL_SHA256)
#define FIT_HASH_ALGO "sha256"
#elif defined(CONFIG_SPL_CRC32)
#define FIT_HASH_ALGO "crc32"
#endif
#endif
#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
#define HAS_FIT
#endif
/ {
binman: binman {
multiple-images;
@@ -13,6 +43,126 @@
#ifdef CONFIG_SPL
&binman {
#ifdef HAS_FIT
fit_template: template-1 {
type = "fit";
#ifdef CONFIG_ARM64
description = "FIT image for U-Boot with bl31 (TF-A)";
#else
description = "FIT image with OP-TEE";
#endif
#address-cells = <1>;
fit,fdt-list = "of-list";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,align = <512>;
images {
u-boot {
description = "U-Boot";
type = "standalone";
os = "u-boot";
arch = FIT_ARCH;
compression = FIT_UBOOT_COMP;
load = <CONFIG_TEXT_BASE>;
entry = <CONFIG_TEXT_BASE>;
u-boot-nodtb {
compress = FIT_UBOOT_COMP;
};
#ifdef FIT_HASH_ALGO
hash {
algo = FIT_HASH_ALGO;
};
#endif
};
#ifdef CONFIG_ARM64
@atf-SEQ {
fit,operation = "split-elf";
description = "ARM Trusted Firmware";
type = "firmware";
arch = FIT_ARCH;
os = "arm-trusted-firmware";
compression = "none";
fit,load;
fit,entry;
fit,data;
atf-bl31 {
};
#ifdef FIT_HASH_ALGO
hash {
algo = FIT_HASH_ALGO;
};
#endif
};
@tee-SEQ {
fit,operation = "split-elf";
description = "TEE";
type = "tee";
arch = FIT_ARCH;
os = "tee";
compression = "none";
fit,load;
fit,entry;
fit,data;
tee-os {
optional;
};
#ifdef FIT_HASH_ALGO
hash {
algo = FIT_HASH_ALGO;
};
#endif
};
#else /* !CONFIG_ARM64 */
op-tee {
description = "OP-TEE";
type = "tee";
arch = FIT_ARCH;
os = "tee";
compression = "none";
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
tee-os {
};
#ifdef FIT_HASH_ALGO
hash {
algo = FIT_HASH_ALGO;
};
#endif
};
#endif /* CONFIG_ARM64 */
@fdt-SEQ {
description = "fdt-NAME";
compression = "none";
type = "flat_dt";
#ifdef FIT_HASH_ALGO
hash {
algo = FIT_HASH_ALGO;
};
#endif
};
};
configurations {
default = "@config-DEFAULT-SEQ";
@config-SEQ {
description = "NAME.dtb";
fdt = "fdt-SEQ";
#ifdef CONFIG_ARM64
fit,firmware = "atf-1", "u-boot";
#else
fit,firmware = "op-tee", "u-boot";
#endif
fit,loadables;
fit,compatible;
};
};
};
#endif /* HAS_FIT */
simple-bin {
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
@@ -33,143 +183,15 @@
};
};
#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
fit: fit {
#ifdef CONFIG_ARM64
description = "FIT image for U-Boot with bl31 (TF-A)";
#else
description = "FIT image with OP-TEE";
#endif
#address-cells = <1>;
fit,fdt-list = "of-list";
#ifdef HAS_FIT
fit {
filename = "u-boot.itb";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,align = <512>;
offset = <CONFIG_SPL_PAD_TO>;
images {
u-boot {
description = "U-Boot";
type = "standalone";
os = "U-Boot";
#ifdef CONFIG_ARM64
arch = "arm64";
#else
arch = "arm";
#endif
#if defined(CONFIG_SPL_GZIP)
compression = "gzip";
#elif defined(CONFIG_SPL_LZMA)
compression = "lzma";
#else
compression = "none";
#endif
load = <CONFIG_TEXT_BASE>;
entry = <CONFIG_TEXT_BASE>;
u-boot-nodtb {
#if defined(CONFIG_SPL_GZIP)
compress = "gzip";
#elif defined(CONFIG_SPL_LZMA)
compress = "lzma";
#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
};
#endif
};
#ifdef CONFIG_ARM64
@atf-SEQ {
fit,operation = "split-elf";
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
os = "arm-trusted-firmware";
compression = "none";
fit,load;
fit,entry;
fit,data;
atf-bl31 {
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
};
#endif
};
@tee-SEQ {
fit,operation = "split-elf";
description = "TEE";
type = "tee";
arch = "arm64";
os = "tee";
compression = "none";
fit,load;
fit,entry;
fit,data;
tee-os {
optional;
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
};
#endif
};
#else
op-tee {
description = "OP-TEE";
type = "tee";
arch = "arm";
os = "tee";
compression = "none";
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
tee-os {
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
};
#endif
};
#endif
@fdt-SEQ {
description = "fdt-NAME";
compression = "none";
type = "flat_dt";
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
};
#endif
};
};
configurations {
default = "@config-DEFAULT-SEQ";
@config-SEQ {
description = "NAME.dtb";
fdt = "fdt-SEQ";
#ifdef CONFIG_ARM64
fit,firmware = "atf-1", "u-boot";
#else
fit,firmware = "op-tee", "u-boot";
#endif
fit,loadables;
};
};
};
insert-template = <&fit_template>;
#else
u-boot-img {
#endif
offset = <CONFIG_SPL_PAD_TO>;
};
#endif
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
@@ -193,10 +215,9 @@
};
};
#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
#ifdef HAS_FIT
fit {
type = "blob";
filename = "u-boot.itb";
insert-template = <&fit_template>;
#else
u-boot-img {
#endif

16
arch/arm/include/asm/arch-rockchip/grf_rk3288.h
View File

@@ -934,21 +934,21 @@ enum {
RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT),
RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
GMAC_SPEED_SHIFT = 0xa,
GMAC_SPEED_MASK = 1,
GMAC_SPEED_10M = 0,
GMAC_SPEED_100M,
RK3288_GMAC_SPEED_SHIFT = 0xa,
RK3288_GMAC_SPEED_MASK = (1 << RK3288_GMAC_SPEED_SHIFT),
RK3288_GMAC_SPEED_10M = (0 << RK3288_GMAC_SPEED_SHIFT),
RK3288_GMAC_SPEED_100M = (1 << RK3288_GMAC_SPEED_SHIFT),
GMAC_FLOWCTRL_SHIFT = 0x9,
GMAC_FLOWCTRL_MASK = 1,
RK3288_GMAC_FLOWCTRL_SHIFT = 0x9,
RK3288_GMAC_FLOWCTRL_MASK = (1 << RK3288_GMAC_FLOWCTRL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
HOST_REMAP_SHIFT = 0x5,
HOST_REMAP_MASK = 1
RK3288_HOST_REMAP_SHIFT = 0x5,
RK3288_HOST_REMAP_MASK = (1 << RK3288_HOST_REMAP_SHIFT),
};
/* GRF_SOC_CON2 */

5
arch/arm/mach-rockchip/rk3288/Kconfig
View File

@@ -5,7 +5,6 @@ choice
config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_JERRY
config TARGET_CHROMEBIT_MICKEY
bool "Google/Rockchip Veyron-Mickey Chromebit"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -28,7 +26,6 @@ config TARGET_CHROMEBIT_MICKEY
config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -41,7 +38,6 @@ config TARGET_CHROMEBOOK_MINNIE
config TARGET_CHROMEBOOK_SPEEDY
bool "Google/Rockchip Veyron-Speedy Chromebook"
select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -54,7 +50,6 @@ config TARGET_CHROMEBOOK_SPEEDY
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select HAS_ROM
select BOARD_LATE_INIT
select TPL
help

2
arch/arm/mach-rockchip/rk3399/Kconfig
View File

@@ -5,7 +5,6 @@ choice
config TARGET_CHROMEBOOK_BOB
bool "Asus Flip C101PA Chromebook (RK3399)"
select HAS_ROM
select ROCKCHIP_SPI_IMAGE
help
Bob is a small RK3299-based device similar in apperance to Minnie.
@@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_BOB
config TARGET_CHROMEBOOK_KEVIN
bool "Samsung Chromebook Plus (RK3399)"
select HAS_ROM
select ROCKCHIP_SPI_IMAGE
help
Kevin is a RK3399-based convertible chromebook. It has two USB 3.0

6
board/rockchip/evb_rk3568/MAINTAINERS
View File

@@ -89,3 +89,9 @@ M: Maxim Moskalets <maximmosk4@gmail.com>
S: Maintained
F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
F: configs/rock-3c-rk3566_defconfig
LCKFB-TaishanPi
M: Jiehui He <jiehui.he@foxmail.com>
S: Maintained
F: configs/lckfb-tspi-rk3566_defconfig
F: arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi

6
board/rockchip/evb_rk3588/MAINTAINERS
View File

@@ -36,6 +36,12 @@ F: configs/orangepi-5-rk3588s_defconfig
F: arch/arm/dts/rk3588s-orangepi-5.dts
F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
ORANGEPI-5-MAX-RK3588
M: Ilya Katsnelson <me@0upti.me>
S: Maintained
F: configs/orangepi-5-max-rk3588_defconfig
F: arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi
ORANGEPI-5-PLUS-RK3588
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained

1
common/spl/Kconfig
View File

@@ -96,6 +96,7 @@ config SPL_MAX_SIZE
config SPL_PAD_TO
hex "Offset to which the SPL should be padded before appending the SPL payload"
default 0x7f8000 if ARCH_ROCKCHIP
default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
default 0x10000 if ARCH_KEYSTONE

1
configs/chromebook_bob_defconfig
View File

@@ -58,7 +58,6 @@ CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y

1
configs/chromebook_kevin_defconfig
View File

@@ -59,7 +59,6 @@ CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y

1
configs/eaidk-610-rk3399_defconfig
View File

@@ -31,7 +31,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/evb-rk3399_defconfig
View File

@@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
# CONFIG_ROCKCHIP_IODOMAIN is not set
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y

1
configs/ficus-rk3399_defconfig
View File

@@ -37,7 +37,6 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/firefly-rk3399_defconfig
View File

@@ -34,7 +34,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/khadas-edge-captain-rk3399_defconfig
View File

@@ -45,7 +45,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/khadas-edge-rk3399_defconfig
View File

@@ -43,7 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/khadas-edge-v-rk3399_defconfig
View File

@@ -45,7 +45,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

78
configs/lckfb-tspi-rk3566_defconfig Normal file
View File

@@ -0,0 +1,78 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-lckfb-tspi"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-lckfb-tspi.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
configs/leez-rk3399_defconfig
View File

@@ -31,7 +31,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/nanopc-t4-rk3399_defconfig
View File

@@ -34,7 +34,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/nanopi-m4-2gb-rk3399_defconfig
View File

@@ -38,7 +38,6 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/nanopi-m4-rk3399_defconfig
View File

@@ -37,7 +37,6 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/nanopi-m4b-rk3399_defconfig
View File

@@ -37,7 +37,6 @@ CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/nanopi-neo4-rk3399_defconfig
View File

@@ -32,7 +32,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/nanopi-r4s-rk3399_defconfig
View File

@@ -32,7 +32,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

89
configs/orangepi-5-max-rk3588_defconfig Normal file
View File

@@ -0,0 +1,89 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-max"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_SF_DEFAULT_BUS=5
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-max.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_AHCI_PCI=y
CONFIG_DWC_AHCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_PHYLIB=y
CONFIG_RTL8169=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

1
configs/orangepi-rk3399_defconfig
View File

@@ -32,7 +32,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/pinebook-pro-rk3399_defconfig
View File

@@ -51,7 +51,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y

1
configs/pinephone-pro-rk3399_defconfig
View File

@@ -47,7 +47,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/puma-rk3399_defconfig
View File

@@ -64,7 +64,6 @@ CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/ringneck-px30_defconfig
View File

@@ -82,7 +82,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y

1
configs/roc-pc-mezzanine-rk3399_defconfig
View File

@@ -45,7 +45,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/roc-pc-rk3399_defconfig
View File

@@ -43,7 +43,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rock-4c-plus-rk3399_defconfig
View File

@@ -49,7 +49,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rock-4se-rk3399_defconfig
View File

@@ -53,7 +53,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rock-pi-4-rk3399_defconfig
View File

@@ -54,7 +54,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rock-pi-4c-rk3399_defconfig
View File

@@ -54,7 +54,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rock-pi-n10-rk3399pro_defconfig
View File

@@ -35,7 +35,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rock-pi-s-rk3308_defconfig
View File

@@ -40,7 +40,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y

1
configs/rock-s0-rk3308_defconfig
View File

@@ -41,7 +41,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y

1
configs/rock960-rk3399_defconfig
View File

@@ -41,7 +41,6 @@ CONFIG_SYS_MMC_ENV_DEV=1
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

1
configs/rockpro64-rk3399_defconfig
View File

@@ -49,7 +49,6 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y

2
doc/board/rockchip/rockchip.rst
View File

@@ -107,6 +107,7 @@ List of mainline supported Rockchip boards:
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
- FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
- Hardkernel ODROID-M1S (odroid-m1s-rk3566)
- LCKFB TaishanPi (lckfb-tspi-rk3566)
- Pine64 PineTab2 (pinetab2-rk3566)
- Pine64 Quartz64-A Board (quartz64-a-rk3566)
- Pine64 Quartz64-B Board (quartz64-b-rk3566)
@@ -158,6 +159,7 @@ List of mainline supported Rockchip boards:
- Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
- Turing Machines RK1 (turing-rk1-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
- Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s)
- Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588)

6
drivers/misc/Kconfig
View File

@@ -104,7 +104,11 @@ config ROCKCHIP_OTP
config ROCKCHIP_IODOMAIN
bool "Rockchip IO-domain driver support"
depends on DM_REGULATOR && ARCH_ROCKCHIP
default y if ROCKCHIP_RK3328 || ROCKCHIP_RK3568
default y if ROCKCHIP_PX30
default y if ROCKCHIP_RK3308
default y if ROCKCHIP_RK3328
default y if ROCKCHIP_RK3399
default y if ROCKCHIP_RK3568
help
Enable support for IO-domains in Rockchip SoCs. It is necessary
for the IO-domain setting of the SoC to match the voltage supplied

69
drivers/net/gmac_rockchip.c
View File

@@ -151,26 +151,51 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct dw_eth_pdata *dw_pdata = dev_get_plat(priv->dev);
struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
struct rk3288_grf *grf;
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
int clk;
switch (priv->phydev->speed) {
case 10:
clk = RK3288_GMAC_CLK_SEL_2_5M;
break;
case 100:
clk = RK3288_GMAC_CLK_SEL_25M;
break;
case 1000:
clk = RK3288_GMAC_CLK_SEL_125M;
break;
default:
debug("Unknown phy speed: %d\n", priv->phydev->speed);
return -EINVAL;
}
if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
switch (priv->phydev->speed) {
case 10:
rk_clrsetreg(&grf->soc_con1,
RK3288_RMII_CLK_SEL_MASK |
RK3288_GMAC_SPEED_MASK,
RK3288_RMII_CLK_SEL_2_5M |
RK3288_GMAC_SPEED_10M);
break;
case 100:
rk_clrsetreg(&grf->soc_con1,
RK3288_RMII_CLK_SEL_MASK |
RK3288_GMAC_SPEED_MASK,
RK3288_RMII_CLK_SEL_25M |
RK3288_GMAC_SPEED_100M);
break;
default:
debug("Unknown phy speed: %d\n", priv->phydev->speed);
return -EINVAL;
}
} else {
switch (priv->phydev->speed) {
case 10:
clk = RK3288_GMAC_CLK_SEL_2_5M;
break;
case 100:
clk = RK3288_GMAC_CLK_SEL_25M;
break;
case 1000:
clk = RK3288_GMAC_CLK_SEL_125M;
break;
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
default:
debug("Unknown phy speed: %d\n", priv->phydev->speed);
return -EINVAL;
}
rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
}
return 0;
}
@@ -401,6 +426,17 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
}
static void rk3288_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct rk3288_grf *grf;
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrsetreg(&grf->soc_con1,
RK3288_GMAC_PHY_INTF_SEL_MASK | RK3288_RMII_MODE_MASK,
RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_RMII_MODE);
}
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3288_grf *grf;
@@ -703,6 +739,7 @@ const struct rk_gmac_ops rk3228_gmac_ops = {
const struct rk_gmac_ops rk3288_gmac_ops = {
.fix_mac_speed = rk3288_gmac_fix_mac_speed,
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
.set_to_rmii = rk3288_gmac_set_to_rmii,
};
const struct rk_gmac_ops rk3308_gmac_ops = {

2
drivers/pinctrl/rockchip/pinctrl-px30.c
View File

@@ -324,7 +324,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
),
};
static struct rockchip_pin_ctrl px30_pin_ctrl = {
static const struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
.grf_mux_offset = 0x0,

2
drivers/pinctrl/rockchip/pinctrl-rk3036.c
View File

@@ -80,7 +80,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
PIN_BANK(2, 32, "gpio2"),
};
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
.grf_mux_offset = 0xa8,

2
drivers/pinctrl/rockchip/pinctrl-rk3066.c
View File

@@ -82,7 +82,7 @@ static struct rockchip_pin_bank rk3066_pin_banks[] = {
PIN_BANK(6, 16, "gpio6"),
};
static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3066_pin_ctrl = {
.pin_banks = rk3066_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066_pin_banks),
.grf_mux_offset = 0xa8,

2
drivers/pinctrl/rockchip/pinctrl-rk3128.c
View File

@@ -171,7 +171,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
.grf_mux_offset = 0xa8,

2
drivers/pinctrl/rockchip/pinctrl-rk3188.c
View File

@@ -105,7 +105,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.grf_mux_offset = 0x60,

2
drivers/pinctrl/rockchip/pinctrl-rk322x.c
View File

@@ -257,7 +257,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.grf_mux_offset = 0x0,

2
drivers/pinctrl/rockchip/pinctrl-rk3288.c
View File

@@ -212,7 +212,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK(8, 16, "gpio8"),
};
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
.grf_mux_offset = 0x0,

2
drivers/pinctrl/rockchip/pinctrl-rk3308.c
View File

@@ -421,7 +421,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = {
IOMUX_8WIDTH_2BIT),
};
static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
.grf_mux_offset = 0x0,

2
drivers/pinctrl/rockchip/pinctrl-rk3328.c
View File

@@ -330,7 +330,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
0),
};
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.grf_mux_offset = 0x0,

2
drivers/pinctrl/rockchip/pinctrl-rk3368.c
View File

@@ -152,7 +152,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.grf_mux_offset = 0x0,

2
drivers/pinctrl/rockchip/pinctrl-rk3399.c
View File

@@ -279,7 +279,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
),
};
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
static const struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.grf_mux_offset = 0xe000,

1
drivers/pinctrl/rockchip/pinctrl-rk3568.c
View File

@@ -345,7 +345,6 @@ static struct rockchip_pin_bank rk3568_pin_banks[] = {
static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
.pin_banks = rk3568_pin_banks,
.nr_banks = ARRAY_SIZE(rk3568_pin_banks),
.nr_pins = 160,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.iomux_routes = rk3568_mux_route_data,

1
drivers/pinctrl/rockchip/pinctrl-rk3588.c
View File

@@ -324,7 +324,6 @@ static struct rockchip_pin_bank rk3588_pin_banks[] = {
static const struct rockchip_pin_ctrl rk3588_pin_ctrl = {
.pin_banks = rk3588_pin_banks,
.nr_banks = ARRAY_SIZE(rk3588_pin_banks),
.nr_pins = 160,
.set_mux = rk3588_set_mux,
.set_pull = rk3588_set_pull,
.set_drive = rk3588_set_drive,

5
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
View File

@@ -532,6 +532,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
(struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
u32 ctrl_nr_pins = 0;
grf_offs = ctrl->grf_mux_offset;
pmu_offs = ctrl->pmu_mux_offset;
@@ -543,8 +544,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
int bank_pins = 0;
bank->priv = priv;
bank->pin_base = ctrl->nr_pins;
ctrl->nr_pins += bank->nr_pins;
bank->pin_base = ctrl_nr_pins;
ctrl_nr_pins += bank->nr_pins;
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {

1
drivers/pinctrl/rockchip/pinctrl-rockchip.h
View File

@@ -503,7 +503,6 @@ struct rockchip_mux_route_data {
struct rockchip_pin_ctrl {
struct rockchip_pin_bank *pin_banks;
u32 nr_banks;
u32 nr_pins;
int grf_mux_offset;
int pmu_mux_offset;
int grf_drv_offset;

2
drivers/pinctrl/rockchip/pinctrl-rv1108.c
View File

@@ -263,7 +263,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
};
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
static const struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
.grf_mux_offset = 0x10,

1
drivers/pinctrl/rockchip/pinctrl-rv1126.c
View File

@@ -381,7 +381,6 @@ static struct rockchip_pin_bank rv1126_pin_banks[] = {
static const struct rockchip_pin_ctrl rv1126_pin_ctrl = {
.pin_banks = rv1126_pin_banks,
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
.nr_pins = 130,
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
.pmu_mux_offset = 0x0,
.iomux_routes = rv1126_mux_route_data,

12
include/configs/px30_common.h
View File

@@ -18,12 +18,14 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
"script_offset_f=0xffe000\0" \
"script_size_f=0x2000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x08300000\0" \
"fdtoverlay_addr_r=0x08400000\0" \
"kernel_addr_r=0x00280000\0" \
"ramdisk_addr_r=0x0a200000\0" \
"kernel_comp_addr_r=0x03e80000\0" \
"fdt_addr_r=0x01e00000\0" \
"fdtoverlay_addr_r=0x01f00000\0" \
"kernel_addr_r=0x02080000\0" \
"ramdisk_addr_r=0x06000000\0" \
"kernel_comp_addr_r=0x08000000\0" \
"kernel_comp_size=0x2000000\0"
#define CFG_EXTRA_ENV_SETTINGS \