colin/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

board: bsh: imx6ulz_smm_m2: Add delay between DRAM read access

Browse Source 
A small delay between DRAM read access with wrong parameters and
reconfiguration is necessary.
Without a delay between DRAM read access and a following reconfiguration
this reconfiguration fails for certain DRAM chips (Nanya).

Signed-off-by: Michael Bode <michael.bode@bshg.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This commit is contained in:
Michael Bode
2025-05-21 11:47:32 +02:00
committed by Fabio Estevam
parent 6c885d9ac6
commit b7b301c906
1 changed files with 3 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
board/bsh/imx6ulz_smm_m2/spl.c
View File

@@ -13,6 +13,7 @@
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/boot_mode.h>
#include <linux/delay.h>
#include <linux/libfdt.h> #include <linux/libfdt.h>
#include <spl.h> #include <spl.h>
#include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-ddr.h>
@@ -65,10 +66,12 @@ static void spl_dram_init(void)
/* Already configured, nothing to do */ /* Already configured, nothing to do */
break; break;
case SZ_256M: case SZ_256M:
udelay(1);
ddr_cfg_write(&bsh_dram_timing_256mb); ddr_cfg_write(&bsh_dram_timing_256mb);
break; break;
case SZ_128M: case SZ_128M:
default: default:
udelay(1);
ddr_cfg_write(&bsh_dram_timing_128mb); ddr_cfg_write(&bsh_dram_timing_128mb);
break; break;
} }