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clocks: qcs404: Add support for I2C clocks

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Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg
2023-02-13 10:19:09 +05:30
committed by Tom Rini
parent d7bcd6ee40
commit b97487db4e
2 changed files with 75 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
arch/arm/mach-snapdragon/clock-qcs404.c
View File

@@ -81,6 +81,36 @@ static const struct bcr_regs emac_ptp_regs = {
.D = EMAC_D,
};
static const struct bcr_regs blsp1_qup0_i2c_apps_regs = {
.cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR,
.cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR,
/* mnd_width = 0 */
};
static const struct bcr_regs blsp1_qup1_i2c_apps_regs = {
.cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
.cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR,
/* mnd_width = 0 */
};
static const struct bcr_regs blsp1_qup2_i2c_apps_regs = {
.cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
.cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR,
/* mnd_width = 0 */
};
static const struct bcr_regs blsp1_qup3_i2c_apps_regs = {
.cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
.cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR,
/* mnd_width = 0 */
};
static const struct bcr_regs blsp1_qup4_i2c_apps_regs = {
.cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
.cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR,
/* mnd_width = 0 */
};
ulong msm_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -171,6 +201,34 @@ int msm_enable(struct clk *clk)
case GCC_ETH_AXI_CLK:
clk_enable_cbc(priv->base + ETH_AXI_CBCR);
break;
case GCC_BLSP1_AHB_CLK:
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
break;
case GCC_BLSP1_QUP0_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR);
clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP1_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP2_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP3_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR);
clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP4_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
default:
return 0;
}

17
arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
View File

@@ -28,6 +28,23 @@
#define BLSP1_UART2_APPS_N (0x3040)
#define BLSP1_UART2_APPS_D (0x3044)
/* I2C controller clock control registerss */
#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030)
#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010)
#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004)
#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004)
#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004)
/* SD controller clock control registers */
#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)