Merge tag 'xilinx-for-v2023.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.07-rc3 .mailmap - Fix Xilinx IDs ZynqMP: - Fix R5 split boot mode - DT fixes - sync with Linux Xilinx: - Enable virtio and RNG support - Enable ADI ethernet phy SPI/Zynq: - Fix dummy byte calculation
This commit is contained in:
Tom Rini
81
.mailmap
81
.mailmap
@@ -17,66 +17,115 @@
|
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|
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Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
|
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Allen Martin <amartin@nvidia.com>
|
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Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com>
|
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Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> <amit.kumar-mahapatra@xilinx.com>
|
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Andreas Bießmann <andreas.devel@googlemail.com>
|
||||
Andreas Bießmann <andreas@biessmann.org>
|
||||
Aneesh V <aneesh@ti.com>
|
||||
Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
|
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Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.com>
|
||||
Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com>
|
||||
Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com>
|
||||
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
|
||||
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
|
||||
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
|
||||
Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
|
||||
Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
|
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
|
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Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
|
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Dirk Behme <dirk.behme@googlemail.com>
|
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Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
|
||||
Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
|
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Fabio Estevam <fabio.estevam@nxp.com>
|
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Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
|
||||
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
|
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Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
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Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
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Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
|
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Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
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Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
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Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com> <izhar.ameer.shaikh@xilinx.com>
|
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Jagan Teki <402jagan@gmail.com>
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Jagan Teki <jaganna@gmail.com>
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Jagan Teki <jaganna@xilinx.com>
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Jagan Teki <jagannadh.teki@gmail.com>
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Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
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Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
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Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
|
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Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
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Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
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John Linn <john.linn@amd.com> <john.linn@xilinx.com>
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Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
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Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
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Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
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Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
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Lukasz Majewski <lukma@denx.de>
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Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
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Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz>
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Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
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Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
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Marek Vasut <marex@denx.de> <marex at denx.de>
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Markus Klotzbuecher <mk@denx.de>
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Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
|
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Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
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Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
|
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Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
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Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
|
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Michal Simek <michal.simek@xilinx.com> <monstr@monstr.eu>
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Michal Simek <michal.simek@xilinx.com> <Monstr@seznam.cz>
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Michal Simek <michal.simek@xilinx.com> <root@monstr.eu>
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Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
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Michal Simek <michal.simek@amd.com> <root@monstr.eu>
|
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Mirza <Taimoor_Mirza@mentor.com>
|
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Mounika Grace Akula <mounika.akula@amd.com> <mounika.grace.akula@xilinx.com>
|
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Mubin Usman Sayyed <mubin.sayyed@amd.com> <mubin.usman.sayyed@xilinx.com>
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Nathalie Chan King Choy <nathalie.chan-king-choy@amd.com> <nathalie.chan-king-choy@xilinx.com>
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Nathalie Chan King Choy <nathalie.chan-king-choy@amd.com> <nathalie@xilinx.com>
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Nava kishore Manne <nava.kishore.manne@amd.com> <nava.manne@xilinx.com>
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Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
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Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
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Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
|
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Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
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Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
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Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
|
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Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
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Prabhakar Kushwaha <prabhakar@freescale.com>
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Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
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Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
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Rajeshwari Shinde <rajeshwari.s@samsung.com>
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Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
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Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
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Ravi Patel <ravi.patel@amd.com> <ravi.patel@xilinx.com>
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Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
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Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
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Rohit Visavalia <rohit.visavalia@amd.com> <rohit.visavalia@xilinx.com>
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Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com>
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Saeed Nowshadi <saeed.nowshadi@amd.com> <saeed.nowshadi@xilinx.com>
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Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> <lakshmi.sai.krishna.potthuri@xilinx.com>
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Sai Pavan Boddu <sai.pavan.boddu@amd.com> <sai.pavan.boddu@xilinx.com>
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Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com>
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Sandeep Paulraj <s-paulraj@ti.com>
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Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com>
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||||
Shaohui Xie <Shaohui.Xie@freescale.com>
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||||
Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com>
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Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> <shubhrajyoti.datta@xilinx.com>
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Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
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Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
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Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
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Stefan Roese <sr@denx.de> <stroese>
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Stefano Babic <sbabic@denx.de>
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Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
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Tom Rini <trini@konsulko.com> <trini@ti.com>
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Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com>
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TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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Wolfgang Denk <wd@denx.de> <wdenk>
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Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
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Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de>
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Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
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Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com>
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Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
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Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
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Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@castor.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@nyx.(none)>
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York Sun <yorksun@freescale.com>
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Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
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Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
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Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
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Wolfgang Denk <wd@denx.de> <wdenk>
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York Sun <york.sun@nxp.com>
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York Sun <yorksun@freescale.com>
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Łukasz Majewski <l.majewski@samsung.com>
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Lukasz Majewski <lukma@denx.de>
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Mirza <Taimoor_Mirza@mentor.com>
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@@ -26,7 +26,7 @@
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};
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chosen {
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bootargs = "earlyprintk";
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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@@ -8,7 +8,7 @@
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#include "zynq-7000.dtsi"
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/ {
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model = "Zynq MicroZED Board";
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model = "Avnet MicroZed board";
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compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
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aliases {
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@@ -19,11 +19,11 @@
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memory@0 {
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device_type = "memory";
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reg = <0 0x40000000>;
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reg = <0x0 0x40000000>;
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};
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chosen {
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bootargs = "earlyprintk";
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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@@ -42,11 +42,6 @@
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status = "okay";
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};
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&uart1 {
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bootph-all;
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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@@ -62,8 +57,41 @@
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status = "okay";
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};
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&uart1 {
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bootph-all;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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};
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&pinctrl0 {
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pinctrl_usb0_default: usb0-default {
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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conf {
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groups = "usb0_0_grp";
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slew-rate = <0>;
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io-standard = <1>;
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};
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conf-rx {
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pins = "MIO29", "MIO31", "MIO36";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
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"MIO35", "MIO37", "MIO38", "MIO39";
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bias-disable;
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};
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};
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};
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@@ -224,7 +224,7 @@
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};
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partition@22A0000 {
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label = "User";
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reg = <0x22A0000 0x1db0000>; /* 29.5 MB */
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reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
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};
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};
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};
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@@ -32,7 +32,8 @@
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#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02
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#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
|
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|
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#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000
|
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#define ZYNQMP_R5_0_TCM_START_ADDR 0xFFE00000
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#define ZYNQMP_R5_1_TCM_START_ADDR 0xFFE90000
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#define ZYNQMP_TCM_BOTH_SIZE 0x40000
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#define ZYNQMP_CORE_APU0 0
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@@ -215,9 +216,14 @@ static void set_r5_start(u8 high)
|
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writel(tmp, &rpu_base->rpu1_cfg);
|
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}
|
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|
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static void write_tcm_boot_trampoline(u32 boot_addr)
|
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static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr)
|
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{
|
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if (boot_addr) {
|
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u64 tcm_start_addr = ZYNQMP_R5_0_TCM_START_ADDR;
|
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|
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if (nr == ZYNQMP_CORE_RPU1)
|
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tcm_start_addr = ZYNQMP_R5_1_TCM_START_ADDR;
|
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|
||||
/*
|
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* Boot trampoline is simple ASM code below.
|
||||
*
|
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@@ -229,12 +235,12 @@ static void write_tcm_boot_trampoline(u32 boot_addr)
|
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* bx r1
|
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*/
|
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debug("Write boot trampoline for %x\n", boot_addr);
|
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writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
|
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writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
|
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writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
|
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writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
|
||||
writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
|
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writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
|
||||
writel(0xea000000, tcm_start_addr);
|
||||
writel(boot_addr, tcm_start_addr + 0x4);
|
||||
writel(0xe59f0004, tcm_start_addr + 0x8);
|
||||
writel(0xe5901000, tcm_start_addr + 0xc);
|
||||
writel(0xe12fff11, tcm_start_addr + 0x10);
|
||||
writel(0x00000004, tcm_start_addr + 0x14);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -247,8 +253,10 @@ void initialize_tcm(bool mode)
|
||||
release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
|
||||
} else {
|
||||
set_r5_tcm_mode(SPLIT);
|
||||
set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
|
||||
set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
|
||||
enable_clock_r5();
|
||||
release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
|
||||
release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
|
||||
}
|
||||
}
|
||||
@@ -326,7 +334,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
|
||||
enable_clock_r5();
|
||||
release_r5_reset(nr, LOCK);
|
||||
dcache_disable();
|
||||
write_tcm_boot_trampoline(boot_addr_uniq);
|
||||
write_tcm_boot_trampoline(nr, boot_addr_uniq);
|
||||
dcache_enable();
|
||||
set_r5_halt_mode(nr, RELEASE, LOCK);
|
||||
mark_r5_used(nr, LOCK);
|
||||
@@ -339,7 +347,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
|
||||
enable_clock_r5();
|
||||
release_r5_reset(nr, SPLIT);
|
||||
dcache_disable();
|
||||
write_tcm_boot_trampoline(boot_addr_uniq);
|
||||
write_tcm_boot_trampoline(nr, boot_addr_uniq);
|
||||
dcache_enable();
|
||||
set_r5_halt_mode(nr, RELEASE, SPLIT);
|
||||
mark_r5_used(nr, SPLIT);
|
||||
|
||||
@@ -48,6 +48,7 @@ CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_RNG=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
@@ -109,6 +110,7 @@ CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_ZYNQMP_POWER_DOMAIN=y
|
||||
CONFIG_RESET_ZYNQMP=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_ARM_DCC=y
|
||||
CONFIG_PL01X_SERIAL=y
|
||||
CONFIG_XILINX_UARTLITE=y
|
||||
@@ -134,3 +136,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
|
||||
@@ -48,6 +48,7 @@ CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_RNG=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
@@ -98,6 +99,7 @@ CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_ADIN=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
@@ -112,6 +114,7 @@ CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_ZYNQMP_POWER_DOMAIN=y
|
||||
CONFIG_RESET_ZYNQMP=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_ARM_DCC=y
|
||||
CONFIG_PL01X_SERIAL=y
|
||||
CONFIG_XILINX_UARTLITE=y
|
||||
@@ -138,3 +141,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
|
||||
@@ -91,6 +91,7 @@ CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_CMD_RNG=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_SMC=y
|
||||
@@ -171,6 +172,7 @@ CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_ADIN=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
@@ -230,6 +232,9 @@ CONFIG_SPLASH_SCREEN=y
|
||||
CONFIG_BMP_16BPP=y
|
||||
CONFIG_BMP_24BPP=y
|
||||
CONFIG_BMP_32BPP=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_PANIC_HANG=y
|
||||
CONFIG_TPM=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
|
||||
@@ -676,7 +676,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
int op_len, pos = 0, ret, i;
|
||||
u32 dummy_bytes = 0;
|
||||
unsigned int flag = 0;
|
||||
const u8 *tx_buf = NULL;
|
||||
u8 *rx_buf = NULL;
|
||||
@@ -689,11 +688,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
|
||||
}
|
||||
|
||||
op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
|
||||
if (op->dummy.nbytes) {
|
||||
op_len = op->cmd.nbytes + op->addr.nbytes +
|
||||
op->dummy.nbytes / op->dummy.buswidth;
|
||||
dummy_bytes = op->dummy.nbytes / op->dummy.buswidth;
|
||||
}
|
||||
|
||||
u8 op_buf[op_len];
|
||||
|
||||
@@ -707,8 +701,8 @@ static int zynq_qspi_exec_op(struct spi_slave *slave,
|
||||
pos += op->addr.nbytes;
|
||||
}
|
||||
|
||||
if (dummy_bytes)
|
||||
memset(op_buf + pos, 0xff, dummy_bytes);
|
||||
if (op->dummy.nbytes)
|
||||
memset(op_buf + pos, 0xff, op->dummy.nbytes);
|
||||
|
||||
/* 1st transfer: opcode + address + dummy cycles */
|
||||
/* Make sure to set END bit if no tx or rx data messages follow */
|
||||
|
||||
Reference in New Issue
Block a user