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gpio: aspeed: Fix incorrect offset of read back register.

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The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.

Fixes: 7ad889b0f3 ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
This commit is contained in:
Billy Tsai
2022-04-13 13:34:51 +08:00
committed by Tom Rini
parent 0b93b7fed6
commit fe2f284270
1 changed files with 2 additions and 2 deletions
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4
drivers/gpio/gpio-aspeed.c
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@@ -211,7 +211,7 @@ static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset
struct aspeed_gpio_priv *priv = dev_get_priv(dev);
const struct aspeed_gpio_bank *bank = to_bank(offset);
u32 dir = readl(bank_reg(priv, bank, reg_dir));
u32 output = readl(bank_reg(priv, bank, reg_val));
u32 output = readl(bank_reg(priv, bank, reg_rdata));
dir |= GPIO_BIT(offset);
writel(dir, bank_reg(priv, bank, reg_dir));
@@ -239,7 +239,7 @@ aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
{
struct aspeed_gpio_priv *priv = dev_get_priv(dev);
const struct aspeed_gpio_bank *bank = to_bank(offset);
u32 data = readl(bank_reg(priv, bank, reg_val));
u32 data = readl(bank_reg(priv, bank, reg_rdata));
if (value)
data |= GPIO_BIT(offset);