Commit Graph

815 Commits

Author SHA1 Message Date
Marek Vasut
476b886a6f pinctrl: renesas: Convert to IS_ENABLED() macro
Use the IS_ENABLED() macro to reduce amount of #ifdef use in the driver
and improve code coverage. With IS_ENABLED() macro, the code is compiled
and then optimized out, which prevents bitrot.

In case no PFC table matches the SoC in use, do not probe the driver
and instead exit with -ENODEV. This should never happen under normal
conditions, because this would mean the driver DT compatible string
match happened, but the list in probe() cannot match the model listed
in match data associated with the compatible string on which the match
did happen.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-29 16:55:31 +01:00
Tom Rini
5cfbf8c364 Merge tag 'v2025.01-rc5' into next
Prepare v2025.01-rc5
2024-12-25 22:31:04 -06:00
Marek Vasut
545208247d pinctrl: renesas: Minimize R8A779H0 V4M PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- INTC/INTC-EX
- MSIOF
- PWM
- SSI

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
a69f8cb9e2 pinctrl: renesas: Minimize R8A779G0 V4H PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
35c5ac0d53 pinctrl: renesas: Minimize R8A779F0 S4 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- INTC-EX
- MSIOF

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
15c51cc62d pinctrl: renesas: Minimize R8A779A0 V3U PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
59c9ca0ba3 pinctrl: renesas: Minimize R8A77995 D3 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
1ee288a6aa pinctrl: renesas: Minimize R8A77990 E3 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC/INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
fa51edbab6 pinctrl: renesas: Minimize R8A77980 V3H PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
a046f58f33 pinctrl: renesas: Minimize R8A77970 V3M PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
d020179cf0 pinctrl: renesas: Minimize R8A77965 M3-N PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
0edacf1a41 pinctrl: renesas: Minimize R8A77960 M3-W and R8A77961 M3-W+ PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
2890251ead pinctrl: renesas: Minimize R8A77951 H3 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN/CANFD
- DU
- INTC-EX
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
7f19150405 pinctrl: renesas: Minimize R8A7794 E2 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN
- DU
- INTC
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
7db1d1fadf pinctrl: renesas: Minimize R8A7792 V2H PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- CAN
- DU
- INTC
- MSIOF
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
6671e9aebd pinctrl: renesas: Minimize R8A7791 M2-W and R8A7793 M2-N PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN
- DU
- INTC
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
2f3bd7ca26 pinctrl: renesas: Minimize R8A7790 H2 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:

- Audio
- CAN
- DU
- INTC
- MSIOF
- PWM
- SSI
- VIN

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
e6e3d70632 pinctrl: renesas: Add Kconfig symbol for conditional build of full PFC tables
By default the pin multiplexing tables used by U-Boot are reduced
to keep the size of the bootloader low. This option allows build of
full pin multiplexing tables the same way they are included in the
Linux kernel. This includes pin multiplexing options for Audio, CAN,
CANFD, DU, INTC, INTC-EX, MSIOF, PWM, SSI, for which there is no
U-Boot driver. This option is disabled by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-25 19:29:47 +01:00
Marek Vasut
4380b31e40 pinctrl: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Tom Rini
9bc62c980d Merge tag 'v2025.01-rc4' into next
Prepare v2025.01-rc4
2024-12-09 16:29:47 -06:00
Paul Barker
3a735cff5f pinctrl: rzg2l: Drop unnecessary scope
In rzg2l_pinconf_set(), there are no new variables defined in the case
statement for PIN_CONFIG_INPUT_ENABLE so no additional scope is needed.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Paul Barker
bba516a772 pinctrl: rzg2l: Support Ethernet TXC output enable
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.

As this signal is be default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Paul Barker
215663f5e4 pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.

rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
check to ensure this is only used on Ethernet interfaces as it is not
supported on the SD & QSPI interfaces.

While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
value for pwr_reg as it is set in every branch of the following if
condition.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Peng Fan
c22bc4019a pinctrl: imx93: support i.MX91
Reuse i.MX93 pinctrl driver for i.MX91, because i.MX91 follows same
design as i.MX93 in IOMUXC controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07 09:07:04 -03:00
Tom Rini
f96e513318 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2024-12-03 12:37:20 -06:00
Quentin Schulz
5bc65f5cab pinctrl: rockchip: allow to build for TPL
A later commit will make use of the pinctrl driver in TPL so let's add
the ability to build the Rockchip pinctrl driver in TPL.

Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Henrik Grimler
e5565c24bb pinctrl: exynos: fix type of count integer
unsigned int count is used to capture return of dev_read_string_count.
When an error occurs dev_read_string_count returns -ve, which can
hence not be handled correctly. Use int instead of unsigned int so
that errors are detected.

Fixes: 16ca80adc5 ("pinctrl: Add pinctrl driver support for Exynos7420 SoC")

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-11-05 14:26:13 +09:00
Tom Rini
e28e70e392 Merge patch series "Support Aspeed SGPIO controller"
Billy Tsai <billy_tsai@aspeedtech.com> says:

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.

Link: https://lore.kernel.org/r/20241016085955.314236-1-billy_tsai@aspeedtech.com
2024-10-29 16:17:47 -06:00
Billy Tsai
4d5510774d ARM: dts: ast2600: Add SGPIO to device tree
Add SGPIO DTS node and enable them for AST2600 EVB.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
2024-10-29 12:12:04 -06:00
Billy Tsai
be298254be ARM: dts: ast2500: Add SGPIO to device tree
Add SGPIO DTS node and enable it for AST2500 EVB.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
2024-10-29 12:12:04 -06:00
Tim Harvey
59382d2cb9 pinctrl: imx: Convert to use livetree API for fdt access
Convert to using livetree API functions.

Without this if livetree is enabled (OF_LIVE) the imx8mq-pinctrl
driver will (silently) fail to probe causing issues with multiple
devices.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2024-10-25 09:07:30 -03:00
Tom Rini
96573a1312 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-10-13 20:25:22 -06:00
Marek Vasut
04395af28f pinctrl: renesas: Synchronize R-Car R8A779H0 V4M PFC tables with Linux 6.10.9
Synchronize R-Car R8A779H0 V4M PFC tables with Linux 6.10.9,
commit 1611860f184a2c9e74ed593948d43657734a7098 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-10-13 23:21:19 +02:00
Marek Vasut
4d84508177 pinctrl: renesas: Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.10.9
Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.10.9,
commit 1611860f184a2c9e74ed593948d43657734a7098 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-10-13 23:21:19 +02:00
Tom Rini
82686e678e Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Assorted Tegra enhancements. Merged with the recent XPL_BUILD changes,
resolve some whitespace issues and fix the name of the new apalis-tk1
env file by Tom.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-10-13 10:43:24 -06:00
Jonas Schwöbel
b515d7ae0d Tegra30: Add funcmux for UART over SD slot
Tegra 3 has UART-E exposable via SD card slot which may be
handy for debugging. This change only adds funcmux part, to
use UART-E on the device you additionally would need:
- set stdout-path to serial@70006400 (uarte)
- configure sdmmc1_dat3_py4 and sdmmc1_dat2_py5 pinmux for
  uarte
- disable or remove sdhci@7800000 node
- enable CONFIG_TEGRA_ENABLE_UARTE in defconfig
- set CFG_SYS_NS16550_COM to NV_PA_APB_UARTE_BASE in device
  header

Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-10-13 17:20:26 +03:00
Tom Rini
47e544f576 Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"
Simon Glass <sjg@chromium.org> says:

When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL

Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.

For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:

   #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)

In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.

This series starts a change in terminology and usage to resolve the
above issues:

- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
  'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
  defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_

It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.

This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.

The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
2024-10-11 12:23:25 -06:00
Simon Glass
5c10c8badf global: Rename SPL_TPL_ to PHASE_
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Simon Glass
c46760d596 global: Rename SPL_ to XPL_
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Simon Glass
371dc068bb drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:48 -06:00
Simon Glass
456bdb70de xpl: Rename spl_phase() to xpl_phase()
Rename this function to indicate that it refers to any xPL phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:47 -06:00
Chris Webb
f4df9f53b7 pinctrl: mediatek: Bind gpio while binding pinctrl
Mediatek pinctrl drivers call mtk_gpiochip_register() to bind the child
gpio controller as part of mtk_pinctrl_common_probe(). This breaks
gpiohog support because the gpio controller is bound too late for
DM_FLAG_PROBE_AFTER_BIND (set while binding hogs) to work.

Move the mtk_gpiochip_register() to mtk_pinctrl_common_bind() and call
this as the .bind method of each of the mediatek pinctrl drivers.

Signed-off-by: Chris Webb <chris@arachsys.com>
2024-10-07 15:09:55 -06:00
Neil Armstrong
58fa520424 pinctr: qcom: sm8250: add special pins pins configuration data
Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8250 SoC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-10-04 14:57:03 +02:00
Julius Lehmann
a9a8f97e00 pinctrl: qcom: add driver for SM8150 SoC
Add pinctrl and GPIO driver for SM8150. Driver code is based on the
similar U-Boot drivers. All constants are taken from the corresponding
Linux driver. This drivers differs from the similar U-Boot drivers,
because SM8150 SoC have different function IDs for the same functions
on different pins.

Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Julius Lehmann <lehmanju@devpi.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-10-04 14:57:01 +02:00
Tom Rini
773f138632 Merge patch series "Arm: npcm: modify npcm8xx boot setting"
Jim Liu <jim.t90615@gmail.com> says:

Modify npcm8xx new boot design.
Correct memory setting and set gpio default value.
2024-09-16 16:43:53 -06:00
Stanley Chu
3aa2eac4f0 pinctrl: npcm8xx: clear all gpio events
Clear all gpio events to avoid unexpected interrupts
during kernel booting.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2024-09-16 16:43:35 -06:00
Sean Anderson
274e0c7299 sandbox: Fix pinmux warnings with non-test devicetrees
The sandbox pinmux driver is used in the non-test devicetree as well as
the test one. I didn't realize this when I modified the driver for
tests, and so broke the regular use case (which only resulted in
warnings). First, making the pinmux and the UART group available
pre-relocation to avoid ENODEV errors. Then, convert the pin groups and
functions to the new style, adding onewire group as well.

Fixes: 7f0f1806e3 ("test: pinmux: Add test for pin muxing")
Closes: https://source.denx.de/u-boot/u-boot/-/issues/2
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-27 11:17:39 -06:00
Sean Anderson
6a087c0182 pinmux: generic: Use ENOENT instead of ENOSYS
ENOSYS should only be used when a subsystem is completely absent.
Convert its use in pinctrl-generic to ENOENT, which better reflects the
error condition (that a function/group/pin is missing).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-08-15 14:26:59 -06:00
Marek Vasut
62b66c39c2 drivers: pinctrl: Remove duplicate newlines
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-07-22 10:53:05 -06:00
Tom Rini
475aa8345a Merge patch series "mediatek: cumulative trivial fix for OF_UPSTREAM support"
Christian Marangi <ansuelsmth@gmail.com> says:

This is an initial series that have all the initial trivial
fixes required for usage of OF_UPSTREAM for the mediatek SoC

This also contains the pcie-gen3 driver and the required tphy
support driver to make it work.

Subsequent series will follow with conversion of the mtk-clk
to permit usage of OF_UPSTREAM and upstream clk ID.

MT7981, MT7986 and MT7988 migration to upstream clock ID
is complete and working on MT7623.

Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590
2024-07-08 11:56:59 -06:00