blog: home logic: flesh out the full staged-inverter time progression

content/blog/DRAFT-2022-05-26-home-built-computation/index.md

@@ -311,7 +311,7 @@ as data arrives into this device, it's immediately inverted, and will later be p
 if we're deliberate with our control signals, we can cascade these inverter devices without issue.
 here's what that looks like over time:
 
-![TODO: EVERY link here is inverted](staged-inverter-chain-clock0.svg)
+![](staged-inverter-chain-clock0.svg)
 
 TODO: rework this paragraph below to explain things left-to-right.
 just prior to this moment, the last core of each buffer was holding S̄1 and S̄0, respectively.
@@ -320,8 +320,18 @@ S̄1 now shows up at the input to the second device. that input, having an inver
 forces its core into 1 - S̄1, or simply, S1.
 the first device is fed new data at this moment, inverting and storing that signal as well.
 
-TODO: show four clock cycles: from data arriving into the element, to data leaving it.
-TODO: need to switch one of these inverters into a strict buffer stage.
+![](staged-inverter-chain-clock1.svg)
+
+![](staged-inverter-chain-clock2.svg)
+
+you can see above that there's current in _every_ loop during this transition.
+it's the single 0 -> 0 core at the end of each device here which prevents
+the state from one device cross its way into the other device at this moment.
+
+![](staged-inverter-chain-clock3.svg)
+
+![](staged-inverter-chain-clock4.svg)
+
 
 in effect, this is a chain of _two_ inverters,
 where each inverter has four clock cycles of latency.
@@ -332,8 +342,9 @@ as our primitive logic gate and arrange it into whatever circuit we want.
 the control signals are nastier than with CMOS, but the concept's there.
 
 
-## TODO: show illustrations of clocked logic, buffered, with a gain stage
-- include simulation results of the gain stage
+## TODO: discuss simulation, show results
+
+## TODO: discuss gain stage
 
 ## TODO: link to my coremem project
 - call for collaboration