blog: home logic: diagram the first clock cycle of the staged inverter

note that all the earlier diagrams were based on CCW currents --
which sort of makes sense, but is needlessly confusing:
these should be CW, in order to have + voltage be on top and ground on
bottom.

ideally, we would rationalize these two things, by having CW CORE
polarization also represent '1' (instead of logic '0').
that's a fair bit of effort, though.

content/blog/DRAFT-2022-05-26-home-built-computation/index.md

@@ -311,7 +311,7 @@ as data arrives into this device, it's immediately inverted, and will later be p
 if we're deliberate with our control signals, we can cascade these inverter devices without issue.
 here's what that looks like over time:
 
-![](staged-inverter-chain-clock0.svg)
+![TODO: EVERY link here is inverted](staged-inverter-chain-clock0.svg)
 
 TODO: rework this paragraph below to explain things left-to-right.
 just prior to this moment, the last core of each buffer was holding S̄1 and S̄0, respectively.