blog: home logic: correct the core parity and begin the staged inverter chain clock diagram
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After Width: | Height: | Size: 32 KiB |
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@ -299,12 +299,27 @@ cores, and leaving just one inverting core:
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differential signals: +Vdd for logic '1' and -Vdd for logic '0'. but this requires either
|
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6 cores per device, or three more-difficult-to-manufacture '8'-shaped cores -->
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notice the wire sections which were previously blue but now red:
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any pulses they carry are sent "into" the core (into the page)
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instead of "out of" the core as before. hence, pulses on the red wires
|
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have a tendency to write logic '1' to the core they feed into,
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whereas the blue wires write logic '0' instead.
|
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|
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as data arrives into this device, it's immediately inverted, and will later be propagated downstream.
|
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if we're deliberate with our control signals, we can cascade these inverter devices without issue.
|
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here's what that looks like over time:
|
||||
|
||||
|
||||
|
||||
TODO: rework this paragraph below to explain things left-to-right.
|
||||
just prior to this moment, the last core of each buffer was holding S̄1 and S̄0, respectively.
|
||||
now we're clearing those cores and dumping those values onto the output wires.
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S̄1 now shows up at the input to the second device. that input, having an inverted winding,
|
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forces its core into 1 - S̄1, or simply, S1.
|
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the first device is fed new data at this moment, inverting and storing that signal as well.
|
||||
|
||||
TODO: show four clock cycles: from data arriving into the element, to data leaving it.
|
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TODO: need to switch one of these inverters into a strict buffer stage.
|
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|
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|
|
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File diff suppressed because it is too large
Load Diff
|
After Width: | Height: | Size: 80 KiB |
Loading…
Reference in New Issue