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blog: home logic: show a buffered inverter stage

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colin 2022-07-12 02:02:15 -07:00
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@ -269,10 +269,14 @@ and therefore nothing downstream of it would be effected by S1's transition.
this hints that we can isolate data transfers by inserting buffer cores into this chain
which are fixed at the '0' state during the CTL1 transition.
![TODO](buffered-inverter-stage.svg)
TODO: 4 element inverter, with the two edges being held low.
![](buffered-inverter-stage.svg)
for brevity i replaced the visual polarizations with their logic values
and whatever way they're transitioning. note that current still _flows_ into the buffers,
it just doesn't do anything. crucially, not current flows out the other end of the buffers.
for brevity i replaced the visual polarizations with their logic values.
we keep the two buffer cores at '0' by driving them with a negative voltage.
not strictly necessary, but the real circuit experiences things like reflections
which would otherwise nudge the buffers away from their set point.
finally, we can tile this group of four cores to construct inverter chains of arbitrary length