blog: home logic: show what it looks like when two inverters are chained together

content/blog/DRAFT-2022-05-26-home-built-computation/index.md

@@ -280,8 +280,14 @@ which would otherwise nudge the buffers away from their set point.
 
 finally, we can tile this group of four cores to construct inverter chains of arbitrary length
 
-![TODO](staged-inverter-chain.svg)
-TODO: 8 element inverter chain. show four clock cycles: from data arriving into the element, to data leaving it.
+![](staged-inverter-chain.svg)
+note that i've annotated only two of the cores as having a state:
+each of these two "inverters" carries only one bit, with the rest of the cores being used as buffers.
+as we mess with the control signal, that state will propagate downstream and eventually leave the inverter.
+here's what that looks like over time:
+
+TODO: show four clock cycles: from data arriving into the element, to data leaving it.
+TODO: VALIDATE THAT WE ACTUALLY NEED FOUR CORES. am i sure we don't need only 3?
 
 in effect, this is a chain of _two_ inverters,
 where each inverter has four clock cycles of latency.