blog: coremem: build the NOR and NOT gate

content/blog/DRAFT-2022-05-26-home-built-computation/index.md

@@ -175,9 +175,69 @@ would be enough to move the core substantially along this curve.
 
 in this way, these core memories from the 60's were already performing 'AND' operations. 
 
-TODO: show a majority gate
+the calibration for this is tricky though. for our purposes, an 'OR' gate provides more reliable operation.
 
-## TODO: show illustrations of clocked logic, with output buffers
+![](a-b-clear-sense-gate.jpg)
+
+imagine the core depicted above is polarized CCW.
+a pulse on either A or B will push it toward the CW polarization.
+then a pulse on CLEAR -- which is wrapped in the opposite direction as A or B -- will push it back into the CCW polarization.
+
+this is a simple OR gate.
+for signals on the wire, we treat a pulse as logic '1', and a lack of a pulse as logic '0'.
+calibration is simpler than the memories from above:
+just tune the signals to be as strong as possible.
+if any '1' arrives to the core, then its state gets flipped to CW, and when we apply the CLEAR signal later we get a pulse
+on the SENSE wire (logic '1').
+if no '1' arrives to the core, then the CLEAR signal does nothing and no pulse is produced at the SENSE wire (logic '0').
+
+if you're keen, you'll notice that the sense wire gets pulsed not only when the CLEAR signal transitions the core from CW to CCW,
+but also gets pulsed (in the opposite direction) when A or B transition the core from CCW to CW: i'll address that later.
+
+for now, consider a slight modification: what if we added _another_ control signal, and inverted the polarization of A and B?
+
+TODO: a-b-set-reset-gate.jpg
+
+the operation of the device now looks like this:
+1. pulse SET to polarize the core CW.
+2. allow some time for a pulse to arrive on either A or B.
+3. pulse RESET to polarize the core CCW, and observe the SENSE wire.
+4. (repeat for the next operation)
+
+this time, the device defaults to logic '1', but if either A or B receive
+a pulse it gets flipped to the logic '0' state before its read.
+in this sense, it's a NOR gate: one of the primitive gates from which we know
+_any_ combinatorial logic can be built from.
+
+in practice, 5 wires through a core may be unwieldy.
+if we remove the 'B' input above, we're left with an ordinary NOT gate.
+so we may prefer to construct our circuitry from 4-wire OR and 4-wire NOT gates instead.
+
+alternatively, if we treat the blue/red wires as data, and the green wires as
+out-of-band control signals, then we don't need separate SET/RESET wires:
+we can remove the RESET wire and do this:
+
+1. apply positive pulse to SET to polarize the core CW.
+2. allow some time for a pulse to arrive on either A or B.
+3. apply _negative_ pulse to SET to polarize the core CCW, and observe the SENSE wire.
+4. (repeat for the next operation)
+
+it's not too crazy: the SET signal is sort of behaving just like a differential clock signal,
+switching from +V to -V to +V to -V ...
+
+
+## Cascaded Logic
+
+so now we've got our primitive logic gates.
+we should be able to assemble them into something greater.
+a good thing to build first would be an inverter chain (maybe even loop it back onto itself to build a ring oscillator).
+just take our clocked inverter, build 3 of these, and wire them in series, right?
+
+TODO: 3-length inverter chain.
+
+not that simple: we have a few stray signals we need to look closer at first (this is the part where i said "i'll address this later").
+
+TODO: show why this doesn't work.
 
 ## TODO: show illustrations of clocked logic, buffered, with a gain stage
 - include simulation results of the gain stage